JPS6016023A - Complementary logic circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a complementary logic circuit, and in particular to a combination of a Mis) transistor and a bipolar transistor or a static induction transistor, which achieves low power consumption and This invention relates to a non-inverting complementary logic circuit that enables high-speed operation.

[Technology background]

Generally, 0-Ml5 type logic circuits have extremely low power consumption, but have low load driving ability and relatively slow operating speed. On the other hand, a polar logic circuit using a semi-polar transistor or the like has a high driving capacity for a load and can be expected to operate at high speed, but has the drawback of high power consumption. Therefore, if a logic circuit that combines the advantages of both of these logic circuits can be constructed, it will be possible to significantly improve the performance of computers and other digital systems.

[Prior art and problems]

Conventionally, a non-inverting logic circuit has been constructed by cascading two 0-MIS type inverter circuits, as shown in FIG. 1, for example. Each 0-M I S type inverter consists of a p-channel M1B transistor Q1 and an n-channel MI8) transistor Q21 and a p-channel Mis) transistor Ql' and an n-channel M
is) constituted by transistor Q2'. The input signal IN is applied to each transistor Ql and Q2 of the first stage inverter.
The inverted output of the first stage inverter is input to the gate of each transistor Ql/ and Q2' of the next stage inverter, and the output signal OUT is applied to the gate of the transistor Q
It is taken from the interconnected drains of l' and Q2'.

In the circuit shown in FIG. 1, when the input signal IN is at a high level, the transistor Q2 of the first stage inverter is turned on, the transistor Q1' of the next stage inverter is turned on, and the output signal OUT becomes high level. Conversely, when the input signal IN is at a low level, the transistor Q1 of the first stage inverter is turned on, the transistor Q2 of the next stage inverter is turned on, and the output signal OUT becomes low level. In this way the first
The circuit shown operates as a non-inverting circuit. And the first
In the circuit shown in the figure, when the input signal IN is at a bulk level, the transistor Qt of the first stage inverter and the transistor Q2 of the next stage inverter are cut off.

When the input signal IN is at a low level, transistor Q2 of the first stage inverter and transistor Q1 of the next stage inverter
' is cut off, so it consumes almost no power in a steady state where the input signal is maintained at a high or low level, and only in a transient state. Therefore, by using the circuit shown in FIG. 1, it was possible to construct a low-power logic circuit.

However, in the conventional type, the transistors Ql, Q2 and Q1' of the inverter in each stage.

Since both Qd are lateral MIS transistors,
There is a disadvantage that current flows through the surface of the semiconductor substrate, resulting in a significantly high on-resistance and a reduction in operating speed due to the load capacitance OL. It has also been considered to increase the channel width in order to reduce the on-resistance in MIS transistors, but increasing the channel width increases the input capacitance, that is, the gate capacitance, and it has not been possible to increase the total operating speed that much. Further, in the conventional circuit, in order to increase the driving capability, the threshold value of each transistor is made small so that the on-side transistors are sufficiently saturated in a steady state. Therefore, in the transition state, a wasteful transient current flows from the power supply (2) to (2) during the on-on state, resulting in an inconvenience that the power consumption of the nine circuits increases.

[Purpose of the invention]

In view of the problems in the conventional type described above, an object of the present invention is to provide a first stage circuit having n-type and p-type Mis) transistors and an npn transistor in a complementary logic circuit.
A complementary type circuit is constructed using a type and an output circuit having a pnp type bipolar transistor or a static induction transistor, and the output circuit is used as an emitter (source).
The object of the present invention is to provide a non-inverting logic circuit that is capable of high-speed operation while consuming extremely low power, based on the concept of a follower-type circuit.

[Structure of the invention]

According to the present invention, the first stage circuit includes an n-type MIS transistor and a p-type MIS transistor, an npn-type bipolar transistor (or an n-type static induction transistor), and a pnp-type bipolar transistor. (or p-type static induction transistor)
The gates of the Mis) transistors are connected to each other to receive an input signal, and the sources of the n-type and p-type Mis) transistors are respectively connected to the npn
It is connected to the bases (gates) of type and pnp type bipolar transistors (n-type and p-type static induction transistors), and the emitters (sources) of each bipolar transistor (static induction transistor) are connected to each other. This is achieved by providing a complementary logic circuit characterized in that all power is supplied from the drain of each Mis) transistor and the collector (drain) of each bipolar transistor (static induction transistor).

[Embodiments of the invention]

The present invention will be explained in detail below with reference to one drawing.

FIG. 2 shows a complementary logic circuit according to one embodiment of the present invention. The circuit in the figure includes an nWMI transistor Qs having a lateral structure, a p-type MIS transistor Q4 having a lateral structure, an npn transistor Q5 having a vertical structure, and a pnp transistor Qa having a vertical structure, for example. Be equipped. Transistors Q5 and Qs are each, for example, npn
The transistor is a biborder-type bipolar transistor and a pnp-type bipolar transistor. The gate of MIS transistor Q8 and the gate of MIS transistor Q4 are connected to each other and input signal IN is applied thereto. The source of the MIS transistor Q3 is connected to the base of the transistor Q5, and the drain is connected to the high potential side of the power supply. The source of the ~11S transistor Q4 is connected to the base of the transistor Q6, and the drain is connected to the low potential side - of the power supply. An output signal OUT is taken out from the commonly connected emitters of transistors Q5 and Qs. Further, the collectors of the transistors Qs and Qs are respectively connected to the high potential side 1+ of the power supply and the low potential 1llllV- of the power supply. In addition, when normally-off type elements such as bipolar transistors are used as transistors Q5 and Qs, the drains of transistors Q3 and Q4 may be connected as shown by the broken line in FIG.

This connection is not made when normally-on type elements of 5IT= are used as transistors Q5 and Qs.

In the circuit shown in FIG. 2, when the input signal IN is at a high level, the n-type MIS transistor Q3 is turned on and npn
) Pull the base of transistor Q5 to a high level. As a result, the transistor Qi is turned on and the output signal OU
T becomes high level. At this time, both the p-type MIS) transistor Q4 and the pnp) transistor Q6 are in a cutoff state. Conversely, when the input signal IN is at a low level, the p-channel M■S transistor Q4 turns on and F
) Since the base voltage of the pnp transistor Q6 is lowered, the transistor Q6 is also turned on, and the output signal OUT becomes low level. In this case, both the n-channel MIS transistor Q3 and the npn) transistor Qs are cut off.

As is clear from the above description, the circuit of FIG. 2 operates as a non-inverting circuit, but when the input signal IN is at a high level, both transistors Q4 and Qs are cut off,
Since both transistors Q3 and Qs are cut off when the input signal IN is at a low level, almost no power is consumed in the steady state. Also, transistor QI
! Since both Qs and Qs are vertical transistors, the on-resistance can be made considerably low, and high-speed operation can be performed without being affected by load capacitance. In addition, each lateral MIS transistor Q3 and Q4
Since the load on transistors Q5 and Qs becomes extremely light, there is no need to increase the driving capability of each of these lateral Mis transistors Q3 and Q4. Therefore.

Turn on by lowering the threshold voltage of each MIS transistor.
It is not necessary to take a large on state, and it is possible to reduce the wasteful current flowing from the power supply V+ to - during a transient, and the power consumption of the circuit can be extremely reduced. In general, in MIS-FIiT,
There is a phenomenon in which the gate threshold voltage increases greatly as the potential difference between the source and the substrate increases, that is, the substrate effect. In the circuit of FIG. 2, the substrate of the n-channel MNS transistor Q3 is connected to the low potential side V- of the power supply, and the source of the transistor Q3 is connected to the power supply - through the source and drain of the transistor Q4. Therefore, the voltage between the source and the substrate is higher than that of the conventional 0-M15 circuit.

Similarly, the voltage between the source and the substrate of the p-channel MIS transistor Q4 is also low.

Therefore, for example, if a conventional 0-Ml5 circuit and a circuit according to the present invention are mixed on the same chip, a Vtl shift due to the substrate effect will occur.

In the circuit configuration of the present invention, there is almost no problem due to the buffer effect of the vertical transistor.

Also, even in conventional 0-Ml5 circuits, transistors are stacked in multi-input NAND gates.

Although a Vth shift occurs and the operating speed differs depending on the input terminal, the circuit of the present invention has the advantage that even if a multi-input gate is configured, there is no problem due to the same effect.

In the circuit shown in FIG. 2, various transistors such as those shown in FIG. 3 can be used as the transistors Qs+Q6. Figures 3 (a) and (b) use bipolar transistors as each transistor, and Figure 3 (CG)
9 (d) is 81 T (5ta
Tic Induction Transistor
s Electrostatic induction (]1) type transistor) is shown. In this way, as each of the transistors Qs and Qa, it is possible to use not only a normally-off type transistor having a threshold value such as a bipolar transistor, but also a normally-on type transistor such as an SIT. Each transistor Q3.
Even if a normally-on type is used as 0.6, in a steady state, that is, when the input signal is at either a high level or a low level, this should be the cutoff state. becomes possible. Therefore,
By using the circuit shown in FIG. 2, it becomes possible to use normally-on transistors such as SIT, which conventionally have high speed but cannot be used in low power logic. In addition, 5JTI! It is also possible to design it as a normally-off type element.

FIG. 4 schematically shows the structure of the circuit of FIG. 2 formed on a semiconductor substrate. In the configuration shown in the figure, n-type and p-type SI transistors are used as transistors Q5 and Qs, respectively.
T is being used. P-type group (12) An n-type epitaxial layer is formed on the plate 1.

Near the boundary between the n-type epitaxial layer 1fi2 and the p-type substrate 1, an n-shaped buried layer 3 and a p-type buried layer 4 are formed. A p-type MIS-FET (Q4) and an n-type SIT (Qs) are formed on the n-type epitaxial layer 2 above the n-shaped buried layer 3. 81
T is as above. The ten-shaped buried layer 3 is used as a drain, the p medium-sized diffusion layer formed on the n-type epitaxial layer 2 is used as a gate, and the n-type buried layer 3 is formed on the n-type epitaxial layer 2 so as to be surrounded by the p medium-sized diffusion layer. The source is the native diffusion layer. In addition.

A part of the p-type gate diffusion layer of the n-type SIT is used as the drain of the p-type FgT. In this way, p-type F'
By forming a complete mixed pattern of ET and n-type SIT, the degree of circuit integration can be increased. Further, a p-type epitaxial layer 5 is formed on the p-type buried layer 4, and an n-channel FET (
Qll) and p-type 81T (Qs) are formed by the same mixed pattern as described above. The electrodes of each transistor having such a structure are wired as shown in the figure using, for example, an aluminum wiring layer, thereby forming the circuit shown in Figure 2. However, in this case, the SIT is designed as a normally-off type. 5ITf: When designed as a normally-on type, the SIT and MI8-FET are separated so that the gates of the BITs are not connected to each other.

FIG. 5 shows the circuit of FIG. 2 with transistors Q5 and Qs.
It is formed using a bipolar transistor having a vertical structure. For example, the bnpn type transistor Q11 has the n-shaped buried layer 3 as its collector and is disposed on the buried layer 3. It has a vertical structure in which an fcp ten-type ore-type diffusion layer is formed via the --type epitaxial layer 2, and an n-type mineral diffusion layer formed on the p-medium type diffusion layer serves as an emitter. PNP transistor Q6 also has a similar vertical structure. Since the other parts are the same as those in FIG. 4, their explanation will be omitted.

In the structure shown in FIGS. 4 and 5.

A p-type lateral MIS-PET, an n-type vertical transistor, an n-type lateral Mis) transistor, and a p-type vertical transistor are each formed as a mixed pattern, and bipolar transistors or the like are used as the vertical transistors Q5 and Qa. Even in the case where bipolar transistors are used, there is no need for an isolation region to separate these bipolar transistors from other transistors, so the degree of integration of one circuit can be increased.

It becomes possible to simplify the manufacturing process.

FIG. 6 shows an A N D gate circuit as another embodiment of the present invention. The circuit in the figure consists of two
p-channel MIS) transistors Q7 and Qa
, an n-channel MIS transistor Q9 and Q+on connected in series with each other, an npn transistor Q11 having a vertical structure, for example, and a pnp transistor Q12 having a vertical structure, for example. The sources of transistors Q7 and Qa are connected to the bases (gates) of transistors Qu and Q12 and the source of transistor Q1o. One input signal INI (15) is applied to the gate of transistor Q7 and the gate of transistor Q9, and the other input signal IN2 is applied to the gate of transistor Q8 and the gate of transistor Q1o. Emitters (sources) of transistors Qo and Q12
are commonly connected and output signal OUT is taken out.

In the circuit of FIG. 6, input signals INI and IN
When both transistors Q2 and Q2 are at a high level, the n-channel MIS transistors Q9 and Qto are turned on, and therefore the npn transistor Qll is turned on, so that the output signal OUT becomes a high level. On the contrary.

When at least one of the input signals INI or INH is at a low level, either transistor Q7 or QB is turned on to pull up the base voltage of pnp transistor Q+2. Therefore, the transistor Q12 is turned on and the output signal OUT becomes low level. Therefore, the sixth
The circuit shown operates as an AND gate.

FIG. 7 shows an OR gate circuit as still another embodiment of the present invention. The circuit shown in the figure consists of p-channel Mis) transistors Qts and Q14 . n-channel MI8 connected in parallel with each other
) transistors Qta and Q16. And npn type and pnp type transistor Q1? and Qls. The detailed structure and operation of this circuit can be easily inferred from what has been described above with respect to the circuit of FIG. 6, so a description thereof will be omitted.

FIG. 8 is a cross-sectional view showing a specific structure of the two-person OR gate circuit shown in FIG. 7. In the figure, 11 is a p-type substrate, 12 is an n-type epitaxial layer, 13 is an n-type buried layer, and 14 is a p+-type buried layer. p channel M
IS transistors Qls, Q14 and npn
) The transistor Q1 is formed on the epitaxial layer 12 on the n-type buried layer 13. Transistor QCs
The drain of Q14 and the source of Q14 are formed by a common p-type diffusion layer, and the source of transistor Q1g and the base of transistor Qly also share the same p-type diffusion layer. The source of transistor Q1g and the sources of transistors Q15 and Qta are connected to wiring (such as an aluminum wiring layer).
17) - is connected by. n-channel MIS) transistor Q1s, Qta and pnp transistor Q
ss are both formed on the p- type epitaxial layer 15 on the p-type buried layer 14. The drain of transistor Q+s and the drain of transistor Q1g are connected to a common n
A natural type diffusion layer is used, and the source of the transistor Q1s and the base of the transistor Qta share the n type type diffusion layer. In the configuration of FIG. 8, p-channel MIS) transistors Qrs, Q14 and npn-type transistors Q17 are formed as a mixed pattern, and n-channel MIS) transistors Qts, Q+
6 and the pnp type transistor QsB are formed as a mixed pattern, so that a highly integrated element can be constructed. Although FIG. 8 shows the case where bipolar transistors are used as the transistors Q17 and Qls, it is also possible to use SIT or the like as described above, and in that case, the structure is similar to that described above. Since it is obvious, the explanation will be omitted.

〔Effect of the invention〕

(18) According to the present invention, for example, an n-type lateral M
Since a complementary logic circuit is constructed using an initial stage circuit consisting of an IS transistor and a p-type lateral MIS transistor and an output circuit consisting of an npn-type bipolar transistor and a pnp-type bipolar transistor, it is possible to use a normally-on type as a bipolar transistor, etc. Even when a device is used, it consumes almost no current in a steady state, making it possible to construct an extremely low-power logic circuit. Further, by using a transistor having a vertical structure in the output stage, an extremely high-speed logic circuit can be realized without reducing the operating speed due to the influence of load capacitance.

This high speed becomes even more remarkable because the load on the lateral MIS transistor in the previous stage is only the gate or the paste of the vertical transistor in the latter stage, and the load on the lateral MIS transistor is reduced. In addition, in the logic circuit of the present invention, each transistor can be formed as a mixed pattern, and isolation between each transistor is not required (19), so the degree of integration can be extremely high. At the same time, the manufacturing process of the device is simplified.

In summary, according to the present invention, a logic circuit is provided which has low power consumption equal to or lower than that of a 0-M1s circuit, has high speed, a high fan-out number, and can be highly integrated.

[Brief explanation of drawings]

Figure 1 shows 0-tl as an example of a conventional logic circuit.
An electric circuit diagram showing an s-type non-inverting circuit, FIG. 2 is a first embodiment of the present invention.
An electric circuit diagram showing the logic circuit according to the embodiment, FIG. 3 is an electric circuit diagram showing the types of transistors used in the circuit of FIG. 2, and FIGS. 4 and 5 are diagrams of the circuit of FIG. 2. FIG. 6 is a cross-sectional perspective view showing a specific structure; FIG. 6 is an electric circuit diagram showing a logic circuit according to another embodiment of the present invention; FIG.
The figure is an electric circuit diagram showing still another embodiment of the present invention. FIG. 8 is a sectional view showing the structure of the circuit shown in FIG. 6. 1.11...p-type substrate. (20) 2.12...n-type epitaxial layer. 3.13...n-type buried layer. 4.14...p medium buried layer. 5.15...p-type epitaxial layer. Qll Ql'l Q41 Q71 Q81 Qts,
Q10...p channel Mis) transistor. Q21 Qi + Q3+ Q'+ Qto, Qls
, Qta-n channel λ418) transistor. Qs, Qo, Qly... n-type vertical transistor. Q a + Q '2r Q ''...p-type vertical transistor. Patent applicant Fujitsu Limited Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney 1) Yukio Patent attorney Akiyuki Yamaguchi . call

Claims (1)

[Claims] 1. An initial stage circuit having an n-type MIS transistor and a p-type MIS transistor, and an npn-type bipolar transistor (or an n-type static induction transistor)
and a pnp-type bipolar transistor (or p-type static induction transistor),
The gates of each MI8) transistor are connected to each other to receive input signals, and the sources of the n-type and p-type MIS) transistors are connected to the npn-type and pnp-type bipolar transistors (n-type and p-type static induction transistor) and the emitter (source) of each bipolar transistor (static induction transistor).
A complementary logic circuit characterized in that the circuits are connected to each other as an output, and power is supplied to the drain of each MIS transistor and the collector (drain) of each bipolar transistor (electrostatic induction transistor). 2. The complementary logic circuit according to claim 1, wherein the bipolar transistor or the electrostatic induction transistor is a vertical type transistor.