JPS60159787A - Display memory control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Lost! The present invention relates to a display memory control method, and more particularly to a display memory control method in which image data is developed in a display memory using a bitmap method.

A display system that displays images including characters and figures using the bitmap method on a display device that requires display refresh, such as a cathode ray tube (CRT), uses the pixel data that forms all the pixels that make up the display screen. is expanded into display memory. This display memory is generally constituted by a RAM.

When the resolution of a display image is improved, the time required to develop all image data into the display memory becomes longer in proportion to the square of the resolution. Also, in order to maintain a predetermined flicker-free image quality, write accesses to the display memory preferably avoid read periods to the display device.

Conventionally, display memory (video RAM) is controlled by a display control device (CRT) independently of system (host computer) control.
In most cases, the system is managed by a controller (controller). In such a system, writing to the display memory is performed in periods not involved in display, ie, blanking periods and blanking periods, avoiding the effective display period of the image signal. Due to this limitation on the writing period, a system with high image quality requires time to develop image data for one screen.

If write access is performed by interrupting the display period in order to shorten the development time, the display will flicker and the display quality will deteriorate.

As a conventional technology that satisfies both of these requirements,
``Time-sharing usage of display memory j'' described in Publication No. 6782
There is. This divides the display period of one pixel into two subcycles, one of which reads out the display memory.
On the other hand, it is used for writing. However, systems that require high resolution must use circuit elements that can operate at extremely high speeds, which is currently difficult to achieve due to hardware conditions.

Since the bitmap method can handle both characters and graphics, it is advantageous for displaying images containing a mixture of both characters. However, with the current state of technology, only RAM with an addressable area of about 128 bytes can be used as display memory, so a system that can use a single VRAM chip to handle various modes in addition to the mixed character/graphic mode has not been realized. Not yet. Using multiple VRAM chips allows various modes to be implemented, but complicates address calculations across multiple areas and increases the time required to do so.

1-Decoy It is an object of the present invention to provide a display memory control method that can overcome the drawbacks of the prior art and display high-resolution images on a display device with good display quality.

1-Makoto The configuration of the present invention will be described below based on one embodiment.

Referring to FIG. 1, in a system to which the display memory control method according to the present invention is applied, a display device IO that requires display refreshing, such as a CRT, is connected to a display control device (C
RTC) 12 to the system bus 14. The system bus 14 also includes a first display memory (V
A RAM) IB, a second display memory 24, and a system memory 18 are connected, and the bus 14 is connected to a central processing unit (CPU) 20 as a post machine.

As can be seen from FIG. 2, either one of the VRAMs 1B and 24 can be selectively accessed by the CPU 20, forming a memory space 26 equivalent to the system memory 18. For example, as shown in Figure (a), VR
AM 1θ can be placed in the accessible memory space A 4m of the CPt 120, and the VRAM 24 can be placed in the accessible space A by switching memory banks as shown in FIG. VRAM lft and 2
4, and system memory 18 collectively form one memory space 2B, a part 16 of which is used as VRAM II and #2 for storing image data, and other areas are used, for example, for bitmap 18a and system work area +8b. etc., are used for data processing by the CPU 20.

According to Kimio, when displaying an image on the CRT 10, the CPU 20 first accesses the VRAM 1B as shown in FIG. 2(a). It is placed in space A, and display data for one screen is written therein. Next, the GPU 20 performs memory puncture switching, and as shown in FIG.
AM 18 outside access space A, and the other VRA
M, that is, VRAM 24 in this example, is placed in access space A.

At that time, the same contents as the contents of VRAM +8 are stored in VRAM.
It will also be expanded on the 24th. Therefore, CRTCI2 uses VRAM
The image data stored in 16 is read out and transferred to the CRT.
10 and display it there.

When the CPU 20 updates the display image data, it rewrites the image data in the VRAM 24 in the access space A. When this rewriting is completed, the CP
U 20 removes VRAM 24 from access space A, switches VRAM 1B to be placed in access space A, and displays the stored data of VRAM 24 on CRT 10. Note that when displaying the contents of one VRAM, it is not necessarily necessary to place the other VRAM in the access space A. In other words, placing the other VRAM in access space A only when updating display data is required is C.
This is advantageous in that it prevents the PU 20 from rewriting the contents of the VRAM when unnecessary.

As shown in FIG. 3, the VRAMs 1B and 24 include a RAM 100 that stores image data for one screen, an interface (I/F) 102 with the system bus 14,
Display output data buffer (BF) 104 and parallel/serial (
P/S) conversion unit 124, GDCI/F 10fl,
It consists of a display address buffer 110 and an inverter 108. From system bus 14, address lines 112.
It is interfaced with a data line 114° and a control signal line 118, and display image data is output in bit series to the CRTC 12 via a data line 28.
2 to address line 117. Data line 118 and control signal line 118° Display address line 1209 Display control 111
:)2. and a dot clock signal line 124 to interface with the numbers shown.

As is clear from the figure, VRAM 113 and 24t
±, From the system side, it has the same configuration as a normal memory such as the memory 18, and from the CRTC 12, it has the same configuration as a normal memory. In addition, system bus 1
VRAM from both the 4 side and the CRTC12 side
1B and 24, which may cause contention between them, but this can be avoided by providing a normal bus arbitration circuit. However, since this is not directly related to the understanding of the present invention, the explanation will be omitted.

Display control device (CRTC:) 12 is basically a CRT.
It has a function to control VRAM 10 and a function to control VRAM 1B [and 24]. This is 1 as shown in Figure 4.
Image data control unit (GIIC) 150. Control buff 1522 display address counter 155. Video signal switching synchronous circuit 158° CRT synchronous signal generation circuit 158. It consists of a status buffer 180, an AND gate 154, etc. The system bus 14 is interfaced with a system bus interface 182.

Addresses, data, and control signals from the system bus 14 are passed through the GDC 150 to the GOCI/GOCI/VRAMs 18 and 24, respectively.
Supplied to F 10B. These allow the CPU 20 to develop stroke vector and graph data in the VRAMs 1B and 24. For display address buffer γ110 of VRAM +8 and 24,
A display address is supplied from the display address counter 155, and the image data at the designated VRAM address is read out from the VRAM 16 or 24 and transferred to the CRT 10.

As shown in the figure, the CRT 10 is supplied with the video signal VIDEO from the VRAM IEI or 24 through the video signal switching synchronization circuit 15B, and the horizontal synchronization signal H8YNC is supplied from the synchronization signal generation circuit 158 through the connection line 178.
and a vertical synchronization signal VSYNC, which control (RT 10. Synchronization signal generation circuit 15
8 provides a blanking signal on lead 184 and a blanking signal on lead 12.
4, a dot clock signal is generated. The status of these signals is transmitted to the CPU 20 through the status buffer 160.
can be identified.

Display data output to CRT 10 is VRA
It is alternatively supplied from MI6 or MI24 through the switching synchronization circuit 15+1, but the switching is performed by the system bus 14.
This is done by control buffer 152, which executes display switching commands received from CPo 20 through. This switching is controlled by switching signals EXI and EX2.

Explain the operation. When the system is set to its initial state by the CPU 20, as shown in FIG. VRAM 24 is out of access range. The synchronization signal generation circuit +58 of the CRTC 12 outputs a blanking signal to the signal line 184 in the initial state, and the switching synchronization circuit 15B deactivates the output of the video signal VIDEO.

First, the CPU 20 reads the VRAM 1B and 24. Next, VRAM 2 for CRTCI2
The control buffer 152 instructs the control buffer 152 to select the video signal output from signal line 1 from signal line 1.
Output to 22.

Switching signal EX2 is VRAM 24 no GDc I/F
The l0EI is deactivated and the display address buffer 110 is activated. As a result, VRAM 24 becomes CRTC12
The contents of the memory location of the RAM 100 corresponding to the output address of the display address counter 155 are stored in the buffer 104.
Read out. This is converted into a serial dot video signal by the P/S converter 124 and output to the signal line 28.

This video signal is transmitted to the switching synchronization circuit 156 in the CRTCI2.
The CRT 10 is synchronized with the dot clock signal applied to the signal line 124 from the synchronization signal generation circuit 158.
and displayed as a visible image.

For example, assume that some image data to be displayed is generated or input into the system. If processing is required, the CPU 20 processes the image data in the work area 18b, and outputs 1 to the bitmap 18a and VRA.
6 is replaced by bank switching, and the image data resulting from the processing is developed on the VRAM 18. Further, when there is an instruction to draw a vector or a graph, necessary parameters are set in the GDC 150, and the GOC 150 processes the data in the VRAM 1θ in accordance with the instructions. The end of the process by this 0-unit C150 is CIIHI
: CPo by reading the status of 150
20 detects.

When all the necessary processing is completed and the image data to be output is expanded to the VRAM IEi, the CPU
Operate the 20-channel VRAM 1B and 24-channel bank, and
Switch to the state shown in Figure (b). That is, VRA
M16 is removed from access space A, and the other VRAM 24 is placed in access space A if necessary. Next, CPt 120 searches status buffer 180 and determines the timing of each retrace period of synchronization signals H5YNG and VSYNC. Detect. Therefore, during this retrace period, the control buffer 152 is instructed to output a switching signal EXI to the switching synchronization circuit 15B to switch the output of the video signal VIDEO from the VRA)124 to the VRA18 side. At that time, the contents of the VRAM 16 are copied and stored in the VRAM 24 in preparation for the next display data update.

As a result, the display screen on CRT 10 is VRAM
The content is instantly switched to the content read from 1B, and thereafter the image data of VRA 1418 is read out and displayed.

When display data needs to be updated, CPU 20 incorporates the other VRAM, 24 into access space A;
The new display data is developed over the previously stored copy of the current VRAM 1B contents. VRAM 24 to C
VR while display data is being output to RT 10
AM 1B is not subject to any restrictions on display, and C
Po 10 can access VRAM 1B at will during that time. In this way, CPo 20 selects any VRA that is not used for display, except during bank switching.
Image data can be expanded to M, and CRT 1
The display of 0 continues.

Although the illustrated embodiment is an example in which image data is output to a display device, it goes without saying that the idea of the present invention can be effectively applied to a hard copy output device such as a printer.

According to the present invention, when displaying an image on a display device, the system writes display data for one screen into either one of two VRAMs. The VRAM that has finished writing is switched to the other VRAM and its contents are transferred to the CRTlo and displayed, and the system develops new display data in the other VRAM as necessary. By repeating this alternately, display data can be updated and displayed in a shorter time than in the conventional method. Therefore, a high-resolution image can be displayed on the display device with good display quality without display flickering.

Note that before the display data is expanded to VRAM, the amount of expanded data is determined, and the synchronization signal VSYNC or H3YNC is
If it can be expanded within the retrace period of
It may also be expanded to RAM.

In that case, display can be performed even more quickly than in the above-described embodiment.

Furthermore, although two VRAMs are prepared in the illustrated embodiment, the present invention is not necessarily limited to this, and it is possible to provide a larger number of VRAMs and display and update image data by sequentially switching between them. Good too.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing an embodiment of the display memory control method according to the present invention, FIG. 2 is a diagram showing a memory map of the system shown in FIG. 1, and FIGS. 3 and 4 are the same as shown in FIG. 1. FIG. 2 is a block diagram showing a specific configuration example of elements included in the embodiment. , , = 10, , display device 12, , display control device 1B, 24. , V RAM 18, , System memory 20, , CPU 100, , RAM 150, , Image data control section 152, , Control buffer 1511, , Video signal switching synchronization circuit Fig. 1 Fig. 2 i

Claims (1)

[Scope of Claims] 1. Control means for controlling an image display device according to instructions from a host machine and displaying display data on the image display device at a predetermined display timing; and selective control from both the host machine and the control means. and a memory means for storing display data to be displayed on the image display device, and when the control means receives a display instruction from the host machine, the control means reads the memory in synchronization with the display timing. means is made accessible from the control means, and display data is read from the memory means and displayed on the image display device, and the host device stores the display data in the memory means during a period when the memory means is not accessed by the control means. A display memory control method characterized by writing. 2. The system according to claim 1, wherein the memory means includes first and second memories, and the controller stage controls the first and second memories according to instructions from the host machine. one of the first and second memories is made accessible from the host machine and the other from the control means, the host machine writes display data into the one of the first and second memories, and the control means writes display data into the one of the first and second memories; A display memory control method characterized in that display data is read from the other of the first and second memories and displayed on the image display device. 3. Display memory control according to claim 2, wherein the first and second memories are alternately accessed by the host machine and the control means. method.