JPS60157604A - Automatic constant speed correcting device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a device that applies speed control to an object that is to move at a constant speed and automatically corrects its speed offset, and particularly relates to a device that applies phase control in addition to speed control. The present invention relates to a steady-state speed error correction device suitable for controlling objects.

[Background of the invention]

Some steady speed error correction devices have been proposed that perform only speed control on an object and automatically correct the steady speed error.

However, if this speed self-correction was always performed, the control system would fluctuate slightly, and it would take time for the control system to stabilize. Furthermore, if speed self-correction is constantly performed with the speed offset detection sensitivity increased, acceleration correction will always be negative? Due to the addition of deceleration Uramasa, it takes time to stabilize the speed control system.

Therefore, although the desired objective is achieved, it is not necessarily satisfactory and improvements are needed when a fast response is required.

Furthermore, in devices that perform phase-side # in addition to speed control, it is not always possible to perform speed self-correction to the end.
It's not a plan. When the phase control system starts to be applied at the time when the self-correction of the cutting speed is almost completed, the controlled object is shaken by the phase control output, and its speed is momentarily shaken. As a result, the speed self-correction function operates and the reference signal of the speed control system is disturbed, and it takes some time for phase synchronization. For this reason, although the desired phase synchronization cannot be achieved, it is not necessarily satisfactory when a fast response is required, and improvements are needed.

Furthermore, if the phase control system is drawn into a phase synchronization state during this period, the reference signal controlled by speed self-correction is maintained in a disturbed state. In other words, once the phases are synchronized, speed deviations cannot be detected and speed self-correction stops. As a result, the speed control error output voltage is output as a voltage that deviates from the normal value. In this state, the phase control system is brought into synchronization. Therefore, in the phase control system, the synchronization phase deviates from the normal state in order to output a voltage that cancels out the error spiral pressure. In other words, a phase offset will occur. Furthermore, the dynamic range became unbalanced, and phase synchronization was likely to occur even with the slightest disturbance, which was often unsatisfactory.

[Purpose of the invention]

The purpose of the present invention is to overcome the unsatisfactory points of the prior art described above.
It is an object of the present invention to provide a steady speed error correction device that can perform self-correction in an optimal state, stop a speed self-correction function at an optimal timing, and set the timing to start applying phase control.

[Summary of the invention]

The main focus of the present invention is to change the correction speed of self-correction by adding speed change (acceleration component) to the speed self-correction function,
In addition to setting the optimum self-correction state, phase control is started when the speed change component reaches a predetermined value or less.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to Figure 171 and Figure 2. In Figure 1, 1 is a motor which is a controlled object, 2 is a frequency generator, 5 is a speed control circuit, 4 is a speed correction circuit,
5 is a phase control circuit, 6 is an adder, 7 is a drive amplifier, and 8 is a phase detector.

Here, the speed control circuit 6 controls the output signal (
In response to the FG flaw signal, the motor 1 is controlled so that this F0 frequency is always constant. Its composition is
A pulse generator 9 that generates a latch pulse L and a brisset pulse P8q every cycle of the de-G signal. A detection counter 10 that counts how many clock signals (not shown) are present during the fl'G period. A latch circuit i1. that holds this count value. V.A.
Henhouki 12. It is comprised of a preset circuit 13 that provides an initial value for the detection counter 10.

The shunting speed correction circuit 4 includes a measurement counter 14 that accurately measures the same period of the FG. Latch circuit 15゜Acceleration detector 1 further calculates acceleration from the information of this latch circuit 15
6. Further, a speed error detector 1Z detects the periodic error of the FG flaw signal from the latch circuit 15, and a target value generating section 1B provides a target value to this detector 17.

Reference preset value generation section 19. It is composed of a digital adder 20 and a switch 21.

Further, the phase control circuit 5 includes a control counter 22 . Latch circuit 23. D
/Ai converter 24 and switch 25.

Next, the operation will be explained. Speed control operation The speed control operation of the motor 1 according to step B will now be explained.

In other words, the de-G signal generated in proportion to the rotation of motor 1 is
First, a latch pulse L and a preset pulse ps which are applied to the pulse generator 9 and control the operation of the detection counter 10 and the latch circuit 11 are output. The detection counter 10 is preset to a value instructed by the preset circuit 16, and starts counting clock signals immediately thereafter.

How would you describe this situation in analog form? 2) as shown in Figure 14). This count value N is taken into the latch circuit 11 and held at the latch node L that accompanies the next FG large input. This held information is converted into a voltage by the D/A converter 12 in the next stage, and is applied to the motor 1 via the adder 6 and the drive amplifier 7.

Next, the operation of the speed correction circuit 4 will be explained. Measurement counter 1
4. Latch circuit 15. is controlled by the latch pulse L from the pulse generator 9 and the precerat pulse pS,
For this reason, the detection counter 10. It operates in exactly the same way as the latch circuit 11. Here, the preset value of the detection counter 10 is:
Fixed to a specific value.

Here, when the motor 1 is stopped, the switch 21 is in an open state, and the output of the speed error detector 17 is also in a zero state. Now, when the motor 1 starts, the motor speed generally changes as shown in Figure 3. In other words, immediately after the motor 1 starts up, it is in a constant acceleration state for a while (period shown in Figure 3A).

Then the predetermined speed f. As the speed approaches , the acceleration decreases as shown in Figure 176, and soon becomes 0. In this state, the speed is also fixed at a constant value.

At this time, the acceleration detector 16 always detects the acceleration shown in Figure 3. As is well known in the art for detecting acceleration (it is sufficient to detect changes in speed, the configuration of the acceleration detector 16 is shown in Figure 6, which will be described later). The detector 16 closes the switches 21 and 25 to turn on.At the same time, the speed error detector 17 starts operating and the F from the latch circuit 15 is turned on.
The cycle measurement value T of the Cx signal is held, and it is compared with the target value T0 from the target value generating section 1B, and an error ΔT of ΔT s T -To is applied to the digital adder 20.

If the information from the latch circuit 15 is held here, the switch 21 returns to its open width. This ΔT is a periodic error expressed as a clock count value.

As a result, the digital knife 20 adds the reference preset value Np and ΔT and prints the result in the preset circuit 13. The operation at this time is shown in Figure 4. (2) in the same figure represents the count value N of the detection counter 10. As mentioned above, when the periodic error is +△T, the brisser toy direct is set to Np. to (Np + ΔT). As a result, when the count value of the detection counter 10 is latched from the next FG multiplied signal, the count value will be larger than the previous one by △T. In other words, the output voltage after D/A conversion will be slightly higher ( , motor 1 rotates a little faster and approaches the target value. (,
IF5 diagram) In the above operation, the phase control circuit 5 becomes effective after the switch 25 is closed. The operation of this phase 1ttlJ control circuit 5 will be explained using Figure 6.

First, the measurement counter 22 counts the clock signal (not shown) using the reference signal LEF, and the counted value M can be expressed as shown in Figure 16 (21).
When the Tach signal (in the figure) is phase-synchronized, it is located approximately at the center of the trapezoidal wave, and the count value of the measurement counter 22 is taken into the latch circuit 26. This information is converted into a voltage signal by the f)/A converter 24 and applied to the adder 6 via the switch 25.

Here, the timing at which the switch 25 closes is the same as when the speed error detector 16 starts operating. In this state where the operation has started, the output of the latch circuit 23 has already been taken in, and even if the speed control system is momentarily disturbed by the output of the phase control circuit 5, it will not affect the speed error detection signal.

In the above explanation, speed error correction is performed only once when the acceleration of the FG signal approaches 0, but in cases of X and A where the speed approaches the target value more accurately, the acceleration becomes 0 again. All you have to do is correct the speed error when you get close. Furthermore, although the timing at which the phase control circuit 5 is activated, that is, the timing at which the switch 25 is closed, is the same as the operation timing for the switch 21, it may also be the timing at which the acceleration approaches the mouth for the second time as described above.

Next, an embodiment of the acceleration configuration circuit 16 is shown in FIG. In the figure, 26 is a latch circuit, 27 is a subtracter, 28 is a comparison circuit, and 29 is an acceleration reference value generating section. Here, the latch circuit 26 has the same configuration as the latch circuit 15 described above, and is similarly driven by the pressure latch pulse L. At this time, the latch circuit 26 first takes in the output of the latch circuit 15, and then the latch circuit 15 is controlled to take in the information of the measurement counter 14. The outputs of these latch circuits 15 and 26 &
'L are each input to a subtracter 27, where the difference between the above two outputs is calculated. It is well known that this difference signal is the difference between two consecutive speed signals, and therefore becomes an acceleration signal. The calculated acceleration signal is applied to the next-stage comparison circuit 28, where it is compared with an acceleration reference value.

This acceleration reference value indicates a mouth velocity threshold that determines how close the added return signal is to 0, and is determined by a circuit designer. Therefore, when the acceleration signal becomes less than this acceleration reference value, the output signal is inverted to close the switches 21 and 25.

In the above explanation, the measurement counter 14 has the configuration shown in Figure 1.
Although the latch circuit 15 has been provided in the explanation, if the flow is only performed once to compensate for the speed by detecting the cutting edge speed, the measurement counter 14 and the latch circuit 15 are completely (unnecessary).At this time, the latch circuit 16 latch circuit 11 instead of the output of
You can use the output of

In addition, in the above explanation, the controlled object has been explained as a motor, but the so-called P Li, (PhaseLock Lo
(op) system, the present invention can be applied.

〔Effect of the invention〕

According to the present invention, by using the sword O speed signal as a means for correcting the speed offset of the controlled object, the speed offset is accurately measured in a stable speed state, and this is automatically corrected to accurately achieve the target speed. Can be matched.

, 11° By performing the phase control based on the above acceleration signal, it is possible to perform phase control at the quickest timing without adversely affecting the above speed correction.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an embodiment of the present invention. Figure 2 is a waveform diagram showing the speed 1iIJ control operation in Figure 1. Figure 6 is a characteristic diagram showing the start-up time of the controlled object. Figure 4 is a block diagram. A waveform diagram showing the speed correction operation in Figure 1, Figure 5 is a speed characteristic diagram of the controlled object according to Figure 4, and Figure 6 is a block diagram showing an example of the acceleration detector in Figure 1. It is a diagram. 6... Speed control circuit, 4... Speed correction circuit, 5... Phase control output circuit, 16... Detection counter, 16... Preset circuit, 16... Acceleration detector 1 17. ...Speed error detector. Representative Patent Attorney Akio Taka, 12゜Continued from page 10 Inventor Isao Fukushima Bakyusho, Totsuka-ku, Yokohama Inventor Tetsuo Sakae 20 Inaatsu, Katsuta City

Claims (1)

[Claims] 1. In a speed control device that has a function of detecting a frequency offset and automatically correcting it so that the control frequency of the controlled object automatically approaches the target frequency, the above-mentioned method is used to determine the timing to perform the automatic correction. A steady speed automatic correction device that performs correction by detecting an acceleration component of a control frequency.