JPS60156091A - CRT display system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CRT (Cathode Ray Tube) display system.

Home video games, which are played using home television receivers, are attracting attention. for example,
For a system that controls displays, input devices, etc. using a microcomputer, see Japanese Patent Application Laid-Open No. 53-12573.
It is shown in No. 2.

(First country filing date: April 6, 1978) Video game devices have traditionally been installed and used in play areas, etc., but by using a home television receiver, It is only recently that devices have begun to be developed that can display images on a screen by transmitting information to the computer, and even output audio to enjoy games.

Incidentally, the CRT display system used in such devices generally takes the form of controlling games with a microprocessor.

To put this more concretely, display data sent from the CPU (Central Processing Unit) is stored in a refresh memory as a code, and this code is read out in accordance with the display timing of the CRT and converted into a pattern in a character signal generation circuit. The most common conventional system is to send this pattern data one pit at a time to a CRT via a video circuit. LSI memory is usually used as the refresh memory that constitutes such a system.

By the way, the chip configurations of LSI chips that are currently readily available are limited to 1-bit configurations such as IK×1 bit, 4×1 bit, 16K×1 bit, etc. for 1 tAM. This is because while there is an increasing demand for larger memory capacities, it is difficult to adopt a multi-bit, 1-byte configuration due to restrictions on the number of package pins. Therefore, the CRT screen
For example, in the case of dividing into 4x64"t, storing the display image as a pattern in the refresh memory requires 512 bytes of memory [1 byte, 8 bits (4 pits)]. Therefore, this is divided into 128 bytes. If this were to be implemented using a standard byte IC memory, four IC memories would be required.For systems that require relatively small amounts of memory, such as CRT display systems, the available R
8 if you are trying to configure refresh memory in AM
Using a memory with a byte configuration such as one bit per byte becomes extremely uneconomical, and a refresh memory cannot be configured with only a single chip.

The present invention allows 1-byte data from the CPU to be sent in parallel.
If we convert it into a serial format using the ff of a serial conversion shift register and store it in the refresher memory, we can use a small number of 1-bit configurations that are currently easily available.
This was born out of the idea that a refresh memory can be configured using SI memory and is economical.

That is, an object of the present invention is to realize a CRT display system using fewer LSI parts.

A further embodiment of the present invention to achieve the above object is R,
It has multiple refresh memories corresponding to each color of G and B, and each refresh memory is stored at a predetermined timing from these memories.
- A CRT display circuit that reads out the contents of memory, synthesizes them, and displays them.

The present invention will be explained below with reference to Examples.

FIG. 1 is a block diagram showing the configuration of a CRT display system according to an embodiment of the present invention.

In the figure, 1 is a central processing unit CPU (microprocessor), and 2 is a main memory ROM (read only memory) of the microprocessor, in which a system monitor, application programs, etc. are written.

3 is the working memory RAM (random access memory) of the microprocessor, 4 is the external input port)
I10Port. In this example,
Although the PUI, ROM2, RAM3, etc. are physically integrated, they may be physically independent.

5 is a shift register for parallel-to-serial conversion, and the CPU
The 8-bit configuration display data from I is stored in parallel, and the stored data is sequentially shifted one bit at a time to refresh memories PM, PM.

Send to. 6 is a serial memory configuration for storing patterns (that is, a bit configuration; if the CRT screen is divided into at 64 x 64, 4 x 1 bit memory)
refresh pattern memory PM.

7 is the address controller ADC, CPU
It plays the role of advancing the specified address address of PMl one address at a time according to the command from. A refresh pattern memory PM2.9 having the same configuration as PM8 is its address controller ADC. In this embodiment, two refresh pattern memories PM 1 and PMt are provided, which will be described in detail later. 10 is an oscillation circuit CPG that generates control clock pulses, and a RAM
3° ADCs 7 and 9 control and drive the horizontal and vertical pulse generators. Reference numeral 11 denotes a horizontal/vertical pulse generator 5YNC which generates a horizontal/vertical reference pulse based on the pulse generated by CPGlo. 12 is a pattern memory PMs −
Interface TV, IF, which converts serial data from P Mt into a signal that can be applied to the grid of CRT.
13 is a CRT.

This system will be explained. The CPV1 sends out data to display various characters, symbols, etc. on the CRT according to a program stored in the ROM2.

In this case, in order to apparently increase the data transfer speed to the pattern memory PM for CPU I77+/sh, two refresh pattern memories PM1. P
M. That is, the CPU calculates the coordinates of the display image, refers to the code table, and PMs the pattern data.

While the pattern data is being transferred to the CRT, the previous pattern data stored in the PMt is being transferred to the CRT and displayed on the screen. After displaying the data in PMtrc, the pattern data stored in PM is displayed, and during this time the coordinates of the displayed image with respect to PM are displayed.
Calculate, refer to two-to-two, and also PN of pattern data.

It transfers the information to the destination.

Originally, for vertical scanning in home television receivers, interlaced scanning was performed twice at 1/60 second intervals.
One frame of image is displayed in 1/30 second. Therefore, refresh pattern memory PM
Data is written to 33.33 as shown in Figure 2.
It is performed at a rate of - times per m5 (one frame time).

Data to the CRT 13 is created by adding a synchronization signal to the data serially read out from the fresh memory PM (this is done at TVIF/2).

Here, assuming that the CRT screen is divided into 64 x 64 parts, the time required for one rask scan (horizontal) is approximately 5.
Since the transfer time is 3.3 μs, the transfer is performed at a rate of 12 Mpi)/s. And now, temporarily PM.

Suppose that data of 4 is being sent to the CRT side, it takes 1 frame time, or 33.33 m5, to transfer all 4 bits (4096 bits to be exact) of data. During this time, the CPUI is PM.

The next frame data is written to.

Therefore, the data transfer rate V from P/5SR5 to PM is as follows. Since CPU 1 sends parallel data consisting of 8 bits per byte, if parallel-to-serial conversion is performed at a rate of 123 bits per second, approximately 15 bits per second.
．． It is sufficient to send the data to the P/5SR5 every 4 times. When a typical microprocessor is used, it takes about 16 to 18 μs to send one byte of data P/S to the configuration shift register SR, so it takes about 8 to 18 μs to transfer 4 bits (512 bytes) of data. 2～
It takes 9.2 ms, but it takes 33.2 ms to process one frame of data.
Since it is sufficient to send the data in 33' ms, the remaining 24 to 25 m5 can be used by the CPU to execute various programs other than data transfer. Therefore, by interlacing (a method in which the KCPU transfers the next frame data (and transfers it to the other refresh memory while the video signal is being retrieved from one refresh memory), the processing time of the CP■ can be saved sufficiently. The refresh memory (PM) is also reduced to about 1 in 800m5.
Since it is only necessary to read data once at a time, it is sufficiently practical.

By the way, here is the refresh pattern memory PM+
The IC memory used as ', PM, is a 1-bit IC memory, and using two available memories with a capacity of 4096 words is sufficient as a refresh pattern memory. If we were to use available chips with a byte configuration as in the past, 8 chips would be required since 128 bytes is standard. Therefore, according to the method of the present invention, the configuration of the refresh pattern memory can be simplified and system costs can be reduced.

FIG. 3 is a block diagram showing the case where the present invention is applied to a CRT display system using a home color television receiver.

In the case of color, one color information is red and green.

Since it is composed of a 3-bit blue signal, it is necessary to construct one refresh pattern memory with three RAMs and send out a 3-bit signal to create one video signal.

Since two sets of refresh pattern memories are required to perform interlace processing, a total of six RAMs are required. Each RAM uses a standard IC memory with a 4096 word 1 pit configuration. In addition, R.G.
- The B primary color data can be used as is as a video signal for an RGB system CRT display, but since the NTSC system is used for home television receivers, the color brightness signal (Y signal) is processed by the matrix circuit 14. ) and two color difference signals (R-Y.

Create B-Y). - Except for the color, this embodiment is basically the same as the embodiment shown in FIG. A memory IC with 4096 words of 1-bit configuration is used.

In this way, the present invention can be applied to both black and white and color CRT display systems, but in any case, the basic principle is to immediately convert parallel display data from CPU 1 into serial data as shown in FIG. The data is converted and stored as serial data in the refresh pattern memory, and the display data from the refresh pattern memory is sent to the interface TVIF1 in the same way as in the general method.
2, and the memory used as the refresh pattern memory is naturally a 1-bit IC memory. As a result of using a 1-pit IC memory, it is possible to use a small number of ICs such as one, two, or six in the case of color, which are commercially available and easy to handle.
The memory can be used to configure a refresh pattern memory.

By the way, one C'RT screen is 64 x 64 d0
', in the conventional method, for black and white, 51
'While eight 2x1 sets of memory were required,
According to the present invention, only one memory of 4×1 pit is required.

In the case of an interlace processing method, the conventional method requires 16 memories of 512×1 bits, whereas the present invention requires only two memories of 4×1 bits.

In the case of color, the required number of IC memories is tripled in either case, and the difference in the required number of IC memories between the present invention and the conventional method becomes large.

In addition, if the display resolution is set to 128 x 128 d0', the storage capacity of the pattern memory for Frenosie is 64 x 6.
It will be four times as much as in the case of 4. Therefore, in the conventional method, I
Even if 16 IC memories of K×1 bits are required, according to the present invention, the number of IC memories is 4×1.

Only 4 pieces are needed.

In this way, color images are better than black-and-white images, and images with high resolution are better than those with low resolution.1. Yoo +)
7vyyzJ#Afi-yl-6')K'S' The reduction in cost is large.

The present invention can be applied to CRT display systems in general, such as game machines and educational video equipment.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a CRT display system according to an embodiment of the present invention. FIG. 2 is a time chart thereof. FIG. 3 is a block diagram showing a color CRT display system according to an embodiment of the present invention. FIG. 4 is a block diagram showing the basic principle of the invention. 1...CPU, 2...ROM, 3...RAM, 4
...l10Port, 5...Shift register for parallel/serial conversion, 6, 8...Number turn memo for refresh 1L7f9...Address controller, 1
0...Oscillation circuit, 11...Horizontal and vertical rotation signal generation circuit, 12...Interface, 13...CR
T, 14... Color matrix. Figure 1/[/ Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. A CRT display system characterized by having a plurality of linkage memories corresponding to a plurality of colors.