JPS60154759A - Psk demodulator - Google Patents

Abstract

PURPOSE:To attain stabilized timing of bit synchronism by using two carriers with different phase so as to detect a PSK signal and regenerating a clock signal from a signal squaring each signal. CONSTITUTION:A carrier (a) from a voltage controlled oscillator (VCO) 17 and a quadruple phase PSK signal A are inputted to a multiplier 12, and a signal (c) corresponding to a prescribed phase difference is extracted via a low pass filter (LPF) 13 from the output signal. The signal (c) is inputted to a multiplier 18, squared and a signal (h) eliminating the polarity is obtained. Similarly, a signal h' is obtained. Signals (i), i' as the result of waveform shaping of the signals (h), h' are inputted to an AND circuit 25, a signal (j) being logical product is obtained and fed to a one-shot multivibrator 26 and a phase comparator 27. A switch 28 is driven by the output (k). The phase locked loop is formed by applying an output signal from the phase comparator 27 to the VCO 31 via the switch 28, an LPF 29 and an amplifier 30.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a PSK demodulator, particularly a PSK (Pha
seShift Keying) This invention relates to a psKiR modulator that reproduces carrier waves, clock signals, etc. from a modulated signal to restore digital data.

(Technical Background and Problems) To demodulate a PSK signal, it is necessary to reproduce the carrier wave, clock signal, etc. that are suppressed by their nature.

For this reason, ' conventionally, for example, the received 4-phase PSK signal was
A so-called 4-multiplying method is used in which a predetermined carrier wave is reproduced by erasing 5-phase information by multiplying and then dividing the frequency by 1/4. The quadrupling method is easily affected by the data pattern contained in the received signal2, for example, SINωt
, -CO3ωt, -5INωt, and CO3ωL, the frequency of the reproduced one-pronged transmission wave does not shift (there is a problem that it is difficult to obtain a stable carrier wave).

In addition, when reproducing a clock signal from a signal after detection for bit synchronization, it is difficult to stably form a pulse signal with a duty of 50% for the data bit width, so a simple exclusive logic circuit is required. There was a problem in that it was difficult to obtain a stable clock signal using a phase comparator consisting of, etc.

(Object and structure of the invention) An object of the present invention is to solve the above problems, and
By detecting the SK signal using two carrier waves having different phases, and reproducing the clock signal from a signal obtained by squaring the detected signals.

The purpose is to stabilize the timing of bit synchronization. Therefore, the PSK demodulator of the present invention is as follows.

Two phase detectors that phase detect the PSK signal.

A psK demodulator comprising a clock signal reproducing section that regenerates a clock signal based on the output signal from the phase detector, a multiplication section that squares each output signal from the two phase detectors, and a multiplication section that squares each output signal from the two phase detectors; and a logical sum calculation section that calculates the logical sum of the output signals from the multiplication section, and samples the digital data included in the output signals from the two phase detectors based on the output signal from the logical sum calculation section, respectively. It is characterized by

(Example of the invention) The present invention will be described in detail below based on the drawings.

1 and 2 are explanatory diagrams for explaining the operation of a PSK demodulating device, FIG. 3 is an explanatory diagram for explaining an example of a conventional PSK demodulating device, and FIG. 4 is an explanatory diagram for explaining an example of a conventional PSK demodulating device shown in FIG. 3. , FIG. 5 shows one embodiment of the present invention.

6 and 7 are explanatory diagrams for explaining the operation of one embodiment of the present invention shown in FIG. 5. FIG.

In the figure, l is a quadruple multiplier, 2 is a BPF, 3. 14°14
', 24.24' is a waveform shaper, 4 is 1/4 minute Fmm
, 5.6.26 is one-shot multi-bye break,
7.27 is P-C (phase comparator).

8.28 is a switch, 9.13.13', 23°29
is LPF, 10.22.30 is amplifier, 11°31 is V
Co, 12, 12°, is, is'', 20 is a multiplier, 1
5 and 15° are D-FFs, 16 is a phase shifter, 19 is a differential amplifier, 21 is an exclusive OR circuit (EX-OR), and 25 is an A
Represents an ND circuit.

In FIG. 1, ``■'' and ``■'' in FIG. 2 respectively indicate the phase relationships corresponding to each value in the 4-phase PSK signal.

A total of four values are shown at equal intervals of 90 degrees.

Generally, the signals at each phase shown in the figure are SI.
Nωt, cosωt, -5INωt and -COSωt
It is represented by the shape of

In the figure, ■ and ■ indicate an example of the phase of a carrier wave for reproduction necessary for phase detection. When 45 degrees is used as the illustrated θ, SIN θ=COS θ, which is convenient for detection as described later.

FIG. 2(A) shows an example of a detected output signal waveform obtained by detecting a four-phase PSK signal, and is called an eye pattern. Since digital data needs to be signal-twisted at the position of the maximum amplitude value of the eye pattern, the clock signal for 9 samplings rises or falls at the maximum amplitude position of the eye pattern, for example, as shown by the arrow in Figure 2 (B). A pulse-like signal is required.

The carrier wave regeneration method used in the conventional 4-phase PSK demodulator example shown in FIG. 3 is a so-called 4-multiplying method, and the carrier wave a is regenerated from the 4-phase PSK signal A by means 1 to 4 in FIG. That is, the frequency of the 4-phase PSK signal A is multiplied by 4 by the 4-fold multiplier 1 to eliminate phase information, BP
After passing through F (band pass filter) 2 and extracting a signal of four times the frequency, it is input to a waveform shaper 3. Then, the waveform-shaped signal output from the waveform shaper 3 is input to the 174 frequency divider 4, and a desired carrier wave a whose frequency is divided into L/4 is obtained. However, the quadruple multiplier method is suitable for specific data patterns such as SINωt, -cos as mentioned above.
If a data pattern consisting of ωt, -5INωt and CO8ωt is received, the recovered carrier a
The frequency of the signal may be shifted. Although this problem can be improved by performing so-called quenching to return the BPF 2 to its initial state when the data pattern changes, there is a problem in that it is difficult to match the timing.

Furthermore, the clock signal for the bit-node synchronization used in the conventional device shown in FIG. 3 is reproduced from the detected output signal d after being detected.

This is carried out by 5 to 11 in the figure. That is, the one-shot multi-by-break 5 receives the input detection output signal d.
(d in FIG. 4) forms a pulse signal e (e in FIG. 4) with a predetermined width Ti, and other one-shot signals e.g.
Input to multi-by-break 6 and P-C (phase comparator) 7. The one-shot multi-by-break 6 is retriggerable, and the input pulse signal e
(e in Figure 4) is detected, a pulse signal f (f in Figure 4) having a predetermined width 3, for example, equal to the width TO of the 1-bit data in Figure 4, is generated. , to the switch 8. The switch 8 is constituted by an analog switch, etc., and supplies the signal from the P-C 7 to the LPF (low pass filter) 9 only when the switch pulse signal f is in the ON state.

After the signal from the LPF 9 is amplified by the amplifier 10, it is input to the VCO II, and is output as a clock signal g (g shown in FIG. 4) at a predetermined time interval, as well as a P-C
Supply to 7. This constitutes a PLL loop, and provides a clock signal g synchronized with the signal d. In such a configuration, if the set pulse width of the one-shot multi-by-break 6 changes, a pulse signal with a duty of 50% cannot be obtained, and the EX- There is a problem in that it is difficult to use a simple and stable circuit such as an OR type phase comparator. Also, the fourth
As shown in the figure, the optimum timing of the clock signal is as shown in the figure.
This is because the feedback loop characteristics tend to become unstable due to the phase characteristics of the EX-OR type phase comparator.

Insert a 90 degree phase shifter into the output of VCOII.

Alternatively, there is a problem in that another phase comparator with a wide detection range is required.

The demodulation of the 4-phase PSK signal is known as shown in Fig. 3.
After inputting the phase PSK signal A and the carrier wave a reproduced by the quadrupling method to the multiplier 12, and inputting the output signal from the multiplier 12 to the LPF 13 to extract a predetermined signal component corresponding to the phase difference, the waveform The waveform is shaped by a shaper 14 to obtain a detection output signal d. And, the above-mentioned illustrations 5 to 11
The clock signal g'cD-FF1 reproduced by
5 to obtain a predetermined digital signal from the detected output signal d.
Extract data B. Further, the phase of the carrier wave a is delayed by 90 degrees by the phase shifter 16, and then input to the 2 multiplier 12゛.
LPF 13°, waveform shaper 14' and D-FF 15°
Digital data C is obtained via the .

Therefore, the present invention aims to stabilize the timing of bit synchronization by detecting each PSK signal using carrier waves having different phases and regenerating a clock signal from a signal obtained by squaring each of the detected signals. be. This will be explained below.

First, an outline of how a four-phase PSK signal is demodulated by the apparatus according to the present invention will be explained using FIG.

In order to obtain a detection output signal d, a 4-phase PSK signal A and a carrier wave a output from a VCO 17 constituting a PLL described later are input to a multiplier 12, and an output signal from the multiplier 12 is input to an LPF 13. Then, a signal C (C shown in FIG. 7) of a predetermined frequency component corresponding to the phase difference is extracted. Then, the signal C is input to the waveform shaper 14 to obtain a detection output signal d. Furthermore, digital data B is extracted from the detection output signal d by a clock signal g, which will be described later, which is supplied to the D-FF 15.

Similarly, from the 4-phase PSK signal A and the carrier wave a outputted from the VCO 17 whose phase is delayed by 90 degrees, the 2 multiplier 1'
2°, LPF 13', waveform shaper 14" and D-F
Digital data C is extracted via F15'.

Next, based on FIG. 5, the carrier wave a is
The configuration and operation for playing will be explained in detail.

The carrier wave a output from the VCO 17 mentioned above is converted into a 4-phase PS
It is input to a multiplier 12 together with the K signal A, and the signal obtained by the multiplier 12 is passed through an LPF 13 to extract a signal C (C in FIG. 7) corresponding to a predetermined phase difference. Then, the signal C is inputted to the multiplier 18 and squared to obtain an output signal h (h in FIG. 7) in which the polarity is eliminated, that is, in the form of 5 in 2 θ or cos 2-θ.

Similarly, the phase of the general transmission wave a outputted from the VCO'17 is delayed by 90 degrees and the 4-phase PSK signal 8 are input to the multiplier 12', A signal h' (conventional as shown in FIG. 3) with polarity removed is obtained.

The signal obtained in this way and the signal h' (sin2
θ or Go! 3'θ) to the differential amplifier 19 to generate a difference signal (sin2θ−coszθ) or (coszθ).
2θ-5inλθ) is obtained. Then, the difference signal and the polarity signal p output from the exclusive OR circuit 21 described in the second section are
is input to the multiplier 20.

As mentioned above, the 4-phase PSK signal A is expressed in a form having phases 1 to 2 shown in FIG. and.

The phase of the carrier wave supplied to the multipliers 12 and 12゛ for phase detection described above is determined by θ=4 in Figure 1 (■ and ■).
In the case of 5 degrees, Sln θ - cos θ, so to configure the PLL loop, the above-mentioned differential amplifier 19 is required.
output signal (sin'θ-cos2θ) or (co
s"θ-5in'θ) may be set to zero.

The values of each signal corresponding to each phase in the input phase column (■ to ■) shown in FIG. 6 are the signals c and c' output from the LPF 13.13'' shown in FIG. Since the values of the signals d and d' are as shown in the figure, the value of the signal d and the value of the signal d' are input to the exclusive OR circuit 21, and the value in parentheses in the p column in the figure is calculated. "+" outside the parentheses in the p column indicates positive polarity, "-" indicates negative polarity, and by inputting the polarity signal to the multiplier 20, the polarity obtained by the differential amplifier 19 is obtained. For example, if the polarity of the phase difference signal is hh' = sin2θ-
cos" θ.Then, the output signal of the multiplier 20 is supplied to the VCO 17 via the amplifier 22 and the LPF 23. Thereby, a PLL loop is formed, and the VCO 17 is adjusted to the shape of θ- as shown in FIG. The carrier wave a shown at 45 degrees is supplied to the multiplier 12, and the carrier wave a at 90 degrees
A carrier wave whose phase is delayed is supplied to a multiplier 12'.

Regeneration of a clock signal for bit synchronization will be explained in detail based on FIGS. 5 and 7.

The signals obtained by squaring by the multipliers 18 and 18' shown in FIG. i and signal i' (i, i' shown in Figure 7) are obtained. Signal i and signal i' are input to the AND circuit 25 to obtain a signal j (j shown in Figure 7) which is the logical product. Although it is possible to sample the digital data B and C from the illustrated signals d and d' using the signal j, a PLL circuit is driven to further increase stability and reliability.

Therefore, the signal j is supplied to the one-shot multi-by-break 26 and the PC 27. The one-shot multi-bye break 26 can be retriggered, and the data is changed to 1 by the rising part of the arrow cloth of the signal j in FIG.
A signal k (seventh signal) with a pulse width corresponding to the focus width To
k) shown in the figure, and the switch 282 is activated by the signal k.
For example, to drive an analog switch. The switch 28 is provided to improve the gain of the PLL loop. Then, the output signal from the p-c (phase comparator) 27 is transferred to the switch 28. LPF29 and amplifier 3
0 to the VCO 31, a PLL loop is constructed, and a clock signal g (g shown in FIG. 7) synchronized with the signal 11°h'' is stably and reliably reproduced.

In this way, since the synchronization signal is extracted after squaring the detected signal, it is not possible to use the conventional one-shot signal shown in Figure 3.
Instability when forming a pulse signal with a duty of 50% by the multi-by-break 5 or the like is eliminated, and a phase comparator such as an EX-OR type having a simple configuration can be used.

(Effects of the Invention) As explained above, according to the present invention, a PSK signal is detected using carrier waves having different phases, and a two-phase comparison is performed to reproduce a clock signal from a signal obtained by squaring each of the detected signals. The duty of the synchronization signal (j shown in Figs. 5 and 7) supplied to the device, etc. is 50%, and the phase comparator (P-C2
7) can be used to regenerate the clock signal and sample digital data stably and reliably.

[Brief explanation of the drawing]

1 and 2 are explanatory diagrams for explaining the operation of a PSK demodulating device, FIG. 3 is an explanatory diagram for explaining an example of a conventional PSK demodulating device, and FIG. 4 is an explanatory diagram for explaining an example of a conventional PSK demodulating device shown in FIG. FIG. 5 shows one embodiment of the present invention. 6 and 7 are explanatory diagrams for explaining the operation of one embodiment of the present invention shown in FIG. 5. FIG. In the figure, 12.12' and 18.18' are multipliers. 13.13', 23.29 are LPFs, 24.24'' are waveform shapers, 15.15' are D-FFs, 16 are phase shifters, 30 are amplifiers, 25 are AND circuits, 26 are one-shot multi-byte Break, 27 is P・C (phase comparator)
, 28 represents a switch, and 31 represents a VCO. Patent Applicant: Alps Electric Co., Ltd. Representative Patent Attorney Hiroshi Mori 1) (3 others) 1st ■ ■ 2 Figure C 4 Figure 6

Claims (3)

[Claims] (1) Two phase detectors that phase detect the PSK signal,
A PSK demodulator comprising a clock signal reproducing unit that reproduces a clock signal based on an output signal from the phase detector, a multiplier that squares each output signal from the two phase detectors, and a multiplier that squares each output signal from the two phase detectors; and a logical sum calculating section that calculates the logical sum of the output signals from the multiplier section, and based on the output signal from the logical sum calculating section, the digital data included in the output signals from the two phase detectors are respectively calculated. A PSK demodulator characterized by sampling. (2) PL based on the output signal from the logical sum calculating section
PSK demodulation according to claim 1, comprising a drive section that drives an L circuit, and sampling digital data included in the output signals from the two phase detectors based on the output signal from the PLL circuit. Device. (3) PSK9 according to claim 2, further comprising a switch section that switches a signal supplied to a VCO from a phase comparator forming the PLL circuit based on an output signal from the OR calculation section. Sorrow device.