JPS60154711A - Frequency doubler circuit - Google Patents
Frequency doubler circuitInfo
- Publication number
- JPS60154711A JPS60154711A JP1124984A JP1124984A JPS60154711A JP S60154711 A JPS60154711 A JP S60154711A JP 1124984 A JP1124984 A JP 1124984A JP 1124984 A JP1124984 A JP 1124984A JP S60154711 A JPS60154711 A JP S60154711A
- Authority
- JP
- Japan
- Prior art keywords
- pulse signal
- circuit
- original pulse
- exclusive
- original
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/00006—Changing the frequency
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
- H03K5/1534—Transition or edge detectors
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ）発明の技術分野
本発明はパルス周波数の逓倍回路に係り、特に抵抗とコ
ンデンサとを組み合わせた遅延回路と排他的ＯＲ回路の
みの簡単な回路により、デユ一ティ比が５０％で周波数
が２逓倍のパルス信号を得る周波数２逓倍回路に関する
。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a pulse frequency multiplier circuit, and in particular, the present invention relates to a pulse frequency multiplier circuit, and in particular, a simple circuit consisting of only a delay circuit combining a resistor and a capacitor and an exclusive OR circuit can increase the duty frequency. The present invention relates to a frequency doubling circuit that obtains a pulse signal whose frequency is doubled at a ratio of 50%.
（ｂ）従来技術と問題点
第１図は従来の２逓倍回路の一例を示し、第２図は第１
図の動作を説明するタイムチャートである。端子（ａｌ
から第２図（ａ）に示す如き原パルス信号が排他的ＯＲ
回路１と３に入る。排他的ＯＲ回路１で零電位と排他的
論理和された出力は抵抗Ｒを経てコンデンサＣを充放電
する。この波形は第２図＋ｄｌに示す如（変化し、入力
閾値がｖｔｈで動作する排他的ＯＲ回路２により零電位
と排他的論理和される。この排他的ＯＲ回路２の出力は
第３図（０１で示す如きパルス信号となり、排他的ＯＲ
回路３で原パルス信号（旬と排他的論理和され端子（ｂ
）に第３図中）で示す如きパルス信号となって送出され
る。(b) Prior art and problems Figure 1 shows an example of a conventional doubler circuit, and Figure 2 shows an example of a conventional doubler circuit.
It is a time chart explaining the operation|movement of a figure. Terminal (al
The original pulse signal as shown in Fig. 2(a) is exclusive ORed from
Enter circuits 1 and 3. The output that is exclusive ORed with the zero potential in the exclusive OR circuit 1 charges and discharges the capacitor C via the resistor R. This waveform changes as shown in FIG. It becomes a pulse signal as shown by 01, and exclusive OR
In circuit 3, it is exclusive ORed with the original pulse signal (current) and output to terminal (b
) is sent out as a pulse signal as shown in FIG. 3).
このパルス信号（ｂ）の波形は排他的ＯＲ回路２の入力
閾値ｖｔｈが排他的ＯＲ回路１の出力の中央にないため
、入力パルスの立ち上がりの遅延時間τ１と立ち下がり
遅延時間τ２とが等しくならず、２逓倍された端子（ｂ
ｌのパルス信号はデユーティ比を５０％にすることが不
可能であるという欠点がある。Since the input threshold value vth of the exclusive OR circuit 2 is not in the center of the output of the exclusive OR circuit 1, the waveform of this pulse signal (b) is not the same as the rising delay time τ1 and the falling delay time τ2 of the input pulse. , the doubled terminal (b
The disadvantage of the 1 pulse signal is that it is impossible to set the duty ratio to 50%.
（Ｃ）発明の目的
本発明の目的は上記欠点を除くため、２逓倍したパルス
信号をデユーティ比５０％にすることが可能で、且つ簡
単な回路構成の周波数２逓倍回路を提供することにある
。(C) Purpose of the Invention The purpose of the present invention is to provide a frequency doubling circuit that can make the duty ratio of the doubled pulse signal 50% and has a simple circuit configuration in order to eliminate the above-mentioned drawbacks. .
（ｄ）発明の構成
本発明の構成はパルス周波数の逓倍回路において、原パ
ルス信号に対し１／４周期遅延したパルス信号を作成す
る手段と、該パルス信号作成手段が作成したパルス信号
と前記原パルス信号とを排他的論理和する手段とを設け
、原パルス信号を２逓倍した周波数のパルス信号を得る
ようにしたものである。(d) Structure of the Invention The structure of the present invention includes, in a pulse frequency multiplier circuit, a means for creating a pulse signal delayed by 1/4 period with respect to the original pulse signal, and a pulse signal created by the pulse signal creation means and the original pulse signal. A means for exclusive ORing the original pulse signal and the pulse signal is provided to obtain a pulse signal having a frequency that is twice the original pulse signal.
（ｅ）発明の実施例
第３図は本発明の一実施例を示す回路図で、第４図は第
３図の動作を説明す−るタイムチャートである。端子（
ｅｌから第４図（ｅｌに示す如き原パルス信号が排他的
ＯＲ回路４と６に入る。排他的ＯＲ回路４で零電位と排
他的論理和された出力は抵抗Ｒ１を経てコンデンサＣを
充放電する。この時抵抗Ｒ２がコンデンサＣに並列接続
されているため、排他的ＯＲ回路４の高レベル出力電圧
を見掛は上小さくし、抵抗Ｒ１，Ｒ２とコンデンサＣの
値を調整することにより、排他的ＯＲ回路５の入力波形
をその閾値ｖｔｈに対して第４図（ｇｌに示す如く対称
とすることが出来る。この波形は入力闇値が■ｔｈで動
作する排他的ＯＲ回路５により零電位と排他的論理和さ
れる。従って排他的ＯＲ回路５の出力は原パルス信号（
ｅ）に対し立ち上がりの遅延時間τ３と立ち下がり遅延
時間τ４とが等しく常に一定の１／４周期遅延するパル
ス信号（ｈｌを送出し、排他的ＯＲ回路６で原パルス信
号ｔｅｌと排他的論理和される。この排他的ＯＲ回路６
の出力は第４図ｆｆ）に示す如く原パルス信号（ｅ）に
対し２倍の周期を持つデユーティ比５０％のパルス信号
となる。(e) Embodiment of the Invention FIG. 3 is a circuit diagram showing an embodiment of the invention, and FIG. 4 is a time chart explaining the operation of FIG. Terminal (
From el, the original pulse signal as shown in FIG. At this time, since the resistor R2 is connected in parallel to the capacitor C, the high level output voltage of the exclusive OR circuit 4 is made smaller in appearance, and by adjusting the values of the resistors R1, R2 and the capacitor C, The input waveform of the exclusive OR circuit 5 can be made symmetrical with respect to its threshold value vth as shown in FIG. Therefore, the output of the exclusive OR circuit 5 is the original pulse signal (
e), a pulse signal (hl) whose rise delay time τ3 and fall delay time τ4 are equal and always delayed by a constant 1/4 period is sent, and an exclusive OR circuit 6 exclusive ORs it with the original pulse signal tel. This exclusive OR circuit 6
The output becomes a pulse signal with a duty ratio of 50% and a period twice that of the original pulse signal (e), as shown in FIG. 4 (ff).
（ｆ）発明の詳細
な説明した如く本発明は簡単な回路構成でデユーティ比
５０％のパルス信号を得ることが出来る。(f) Detailed Description of the Invention As described above, the present invention can obtain a pulse signal with a duty ratio of 50% with a simple circuit configuration.
第１図は従来の２逓倍回路の一例を示す図、第２図は第
１図の動作を説明するタイムチャート、第３図は本発明
の一実施例を示す回路図、第４図は第３図の動作を説明
するタイムチャートである。
１．２，３，４，５．６は排他的ＯＲ回路である。
瞥２酊
瞥３昭
″Ｉ＃４酊FIG. 1 is a diagram showing an example of a conventional doubler circuit, FIG. 2 is a time chart explaining the operation of FIG. 1, FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a time chart explaining the operation of FIG. 3. FIG. 1.2, 3, 4, 5.6 are exclusive OR circuits. Glance 2 Drunken Eye 3 Sho''I#4 Drunkenness
Claims (1)
対し１／４周期遅延したパルス信号を作成する手段と、
該パルス信号作成手段が作成したパルス信号と前記原パ
ルス信号とを排他的論理和する手段とを設け、原パルス
信号を２逓倍した周波数のパルス信号を得ることを特徴
とする周波数２逓倍回路。means for creating a pulse signal delayed by 1/4 period with respect to the original pulse signal in the H/L/S frequency multiplication circuit;
A frequency doubling circuit characterized in that the frequency doubling circuit is provided with means for exclusive-ORing the pulse signal created by the pulse signal creation means and the original pulse signal to obtain a pulse signal having a frequency that is twice the original pulse signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1124984A JPS60154711A (en) | 1984-01-25 | 1984-01-25 | Frequency doubler circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1124984A JPS60154711A (en) | 1984-01-25 | 1984-01-25 | Frequency doubler circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60154711A true JPS60154711A (en) | 1985-08-14 |
Family
ID=11772663
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1124984A Pending JPS60154711A (en) | 1984-01-25 | 1984-01-25 | Frequency doubler circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60154711A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62213412A (en) * | 1986-03-10 | 1987-09-19 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Frequency multiplication circuit |
| JPH0281513A (en) * | 1988-09-17 | 1990-03-22 | Rohm Co Ltd | Frequency multiplier circuit |
-
1984
- 1984-01-25 JP JP1124984A patent/JPS60154711A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62213412A (en) * | 1986-03-10 | 1987-09-19 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Frequency multiplication circuit |
| JPH0281513A (en) * | 1988-09-17 | 1990-03-22 | Rohm Co Ltd | Frequency multiplier circuit |
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