JPS60151775A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To reduce burden of software and make synchronization accurately by starting a program cycle by a clock signal from a clock device commanded by one of plural processors. CONSTITUTION:Start stop control and setting control of period of generation of clock signals CL of a clock device 9 are made by a master CPU1. Period of the clock signals CL is set to a period longer to some degree than any of program cycles of the master CPU1 and slave CPU2-3. The clock signals CL are inputted to each CPU as interruption signals. Each CPU starts its own program processing simultaneously with inputting of the clock signal CL, and when its own program cycle is finished, makes idling operation, and when next clock signal CL is inputted, starts processing of own next program again.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiprocessor system that processes information by operating a plurality of processors simultaneously and in synchronization with each other. This invention relates to a multiprocessor system (hereinafter referred to as MPS) which is equipped with a clock device to reduce the burden on software and to perform synchronization more accurately.

Behind the conventional MPS, master CP LJ and 1 or 2 or more
Mask CPtJ monitors the progress of the programs of other slave CPUs, and when all slave CPUs have finished their programs, each slave CPU is instructed to update the ZUgram. Synchronization is achieved by giving In addition, in MI)S where there is no hierarchical relationship between masks and slaves, all CIs
) U monitors the completion of the program of other CPUs, and synchronization is achieved by updating the program at the Ii% point at which the program of all CPUs is completed.

The means for synchronizing in such MPS is the master C
1) It is configured by software in υ or each CPU, and the wait post method, semaphore method, etc. are known. However, MPS, which is synchronized by software,
In this case, the software becomes complicated and requires a lot of effort to create the software, and if the program cycle in each CPU is shortened, synchronization is lost, resulting in a slow program processing speed.

The present invention aims to solve the above-mentioned problems, and its gist is to connect a plurality of buses 9 via a common bus,
In a multiprocessor system configured to perform program processing while synchronizing each processor, any one of the plurality of processors performs start/stop control and controls the generation cycle of the time-up signal. a clock device that receives a command and sends out a clock signal at a specified period according to the command;
The present invention provides a multiprocessor system characterized in that the program cycle of each of the above programs is started every time the time-up signal (11) is input.

The clock devices among the above components include all hardware clock devices whose cycles can be arbitrarily set.

Next, embodiments embodying the present invention will be described with reference to the accompanying drawings to provide an understanding of the present invention.

FIG. 1 is a diagram showing the configuration when applied to a common memory type MPS.
PUI (2), slave CPU2 (3) connects the common hash (
5) and exchange information via the common memory (6) which is connected to the common bus (5). In addition, each CPU has a local bus (4), (41), (42).
) via local memory (7), (71), (72
) and I10 baud 1-(8), (81), and (82) are connected to the local bus (4), respectively, and a clock device (9) that generates a clock signal CL is connected to the local bus (4). This clock device (9) is subjected to start/stop control and setting control of the generation cycle of the clock signal CL by the mask CPU (j). The period of this clock signal CL is mask CPtJ (1), slave CPUI (
2), the master CPU (1
), the clock signal CL is manually input to each CPU as an interrupt signal, and each CPU starts its own program processing at the same time as the clock signal CL is input, and when its own program cycle ends, It is configured to operate in idling mode until the next clock signal CL is input, and when the next clock advance CL is input, it starts its own next program processing again.

When performing sample value control of a robot having 6 degrees of freedom using the MPS configured in this way, for example, slave CPLJI (2) and slave CPU2 (3)
The master CPU (1) is in charge of monitoring the program progress of the slave CPU 1.2 and monitoring foreign products in the slave CPtJ 1.2. Note that the cycle of each CPU is determined by the clock signal CL as described above.

It goes without saying that the period for reading teaching data input from the outside during teaching is similarly determined by this clock signal CL.

The teaching and reproduction work procedure for such a six-degree-of-freedom type robot will be explained with reference to FIGS. 2 and 3. here the second
The figure is a flowchart showing the procedure of teaching work.
) indicates the work procedure in the master CPU, and the same 1m (
h) shows the work procedure in slave CPU 1 or 2, and FIG. 3 is a flowchart showing the playback work procedure. It shows the work procedure in slave CPUI or 2.

First, using Figure 2, the operator drives the robot using the operation panel, moves the tip of the robot's wrist along the work trajectory, and calculates each joint angle input corresponding to this work movement. This is done by converting a signal (a signal input from a position detector such as a rotary encoder provided at each joint) into a position coordinate value in a rectangular coordinate system, and storing this value in the common memory 6.

That is, as shown in FIG. 2(a), the mask CPU first determines in step S1 whether or not it has received a teaching signal from the operation panel.

When the signal to start teaching is received, slave cpLJ1
．． The slave CPU 2 is instructed to start the teaching work, and a flag is set in the -1mon memory 6 to indicate that the teaching work is in progress. By setting this flag, it becomes possible to load each joint angle signal obtained through the teaching work into the common memory 6 (S2
). L; l:, S when the signal to start teaching is not received
The process bypasses step 2 and moves to step S3. In step S3, it is determined whether a signal indicating the end of the teaching work has been received from the operation panel. When you receive the termination signal,
Slave CPU1. Step 34) instructs the slave CPU 2 to end the teaching work and accesses the common memory 6 to reset the flag indicating the teaching state. Further, in step S5, the master CPU performs teaching data (a position coordinate value signal indicating each joint angle corresponding to each work trajectory) which is teaching coordinate data of the work trajectory stored in the common memory 6, CPU], , is stored in the common memory 6 via the slave CPU 2) is transferred to the auxiliary storage device 35), and then the idling operation is performed until the clock signal CL is input (S6)-0 and step S3. If it is determined that the signal indicating the end of the teaching work has not been received, steps 34 and S5 are bypassed to proceed to S6, and the ring operation is performed on the eye until the clock signal CL is manually inputted, and the clock signal CL is With the human power of
Returning to step S1, the program processing from steps S1 to S6 is resumed.

In addition, each slave CPU first searches in S7 whether or not the teaching flag is set in the common memory 6 in accordance with the program shown in the second FI (L,), thereby determining whether or not to perform the teaching operation. to decide. If the teaching operation is possible, it is determined in step S8 whether or not the position teaching switch on the operation panel has been pressed, and if the teaching switch has been pressed, each joint angle signal (X, Y, Z Or wrist direction cosine α, β,
4iN of γ) is input and stored in the common memory G as teaching data. If it is determined in step S7 that teaching is not in progress, if it is determined in step S8 that the teaching switch is not pressed, and if step S9 is completed, the switch SIO is reached and the clock signal CL is input. While idling until
When the signal Cl is inputted, the process returns to the first step S7 of this program and the processing of this program is restarted.

When the teaching work is thus completed, the reproducing work shown in FIG. 3 is subsequently performed. That is, as shown in FIG. 3(a), during the playback operation, the master CPU determines in step Sll whether or not it has received a signal to start playback (play hack) from the operation panel.

When the reproduction start signal is received, the teaching data is transferred from the auxiliary storage device to the common memory 6 again (S12), and at the same time, in S13, the slave CPU and the slave C
The CPU 2 instructs the PU 2 to start the reproducing operation, and sets a flag in the common memory 6 indicating that the reproducing operation is in progress. As a result, the slave CPU I and the slave CPU 2 access the common memory 6 and perform the 100D operation based on the taught data. Subsequently, in S14, it is determined whether or not a second η:end signal has been received from the operation panel.

When a playback end signal is received, the slave cPU1 and slave CPU2 are instructed to end the playback operation, and at the same time a flag set in the common memory 6 is set to indicate that the work is in progress. Reset (S15
). When the above processing is completed, the master CPU
At step 18, the idling operation is performed until the clock signal CL is input, and when the clock signal is input, the process returns to step Sll to restart the program processing from S11 to Si2.

If it is determined in 311 that the signal to start playback has not been received, the process bypasses S12 and S13 and jumps to S14, and if the signal to end playback has not been received in S14, the process in S15 is performed. Detour and jump to S16.

The slave CI) U, which has received the above-mentioned command from the master CPU, causes each axis of the robot to perform a regeneration operation according to the flowchart shown in FIG. 3(b).

That is, in step S17, it is determined whether or not a reproduction operation is in progress. This determination is made by accessing the common memory 6 and referring to whether or not a flag indicating that a reproduction operation is in progress is set. If it is determined that the reproducing operation is in progress, each axis of the robot is servo-controlled based on the teaching data stored in the common memory 6 to perform the reproducing operation (S18), and then in step S19, the clock signal is Idling operation is performed until CI is input.

If it is determined in step 317 that the regeneration operation is not in progress, it means that the regeneration operation has not started or has already ended, and the process jumps to step 319 to perform idling operation and input the clock signal CL. At the same time, the program returns to 317 and restarts the program.

Although the above embodiment shows a configuration in which the present invention is applied to an MPS that has a hierarchical relationship, it can be similarly applied to an MPS that has no hierarchical relationship. In this case, one of the processors is configured to set the clock signal generation cycle of the clock device.

As described above, the present invention provides a multiprocessor system in which a plurality of processors are connected via a common bus and each processor is configured to perform program processing while synchronizing each other. Receives start/stop control and time amplifier signal generation cycle commands from one of the processors,
The MPS is characterized in that it is equipped with a clock device that sends out a clock signal at the specified fixed cycle, and is configured to start a program cycle for each of the programs each time the time-up signal is manually input. Since no software is required to determine the system cycle, the program is simplified, the processing speed of the program can be increased, and synchronization does not occur.

[Brief explanation of drawings]

1) is a block diagram showing the configuration of an embodiment in which the present invention is applied to a common memory type MPS. Figure 2 is a flowchart showing the procedure of teaching work.
15! l (a > shows the work procedure in the mask CPtJ, FIG. 3(b) shows the work procedure in the slave CPIJ 1 or 2, and FIG. (a) is a mask CPt
The work procedure for slave CPtJ is shown in the same figure (b).
This shows the work procedure in step 1 or 2. (Explanation of symbols) 1...Master CPtJ 2...Slave CPtJ
13...Slave CPtJ2 4.111. 42...Local bus 5...Common bus 6...Common memory? , 71.72...Local memory 8.81', 82...I10 boat 9...Clock device CL...Clock signal. Figure 2 (b) ~ too

Claims (1)

[Claims] (11) In a multi-processor system configured to connect a plurality of processors via a common bus and perform program processing while synchronizing each processor, a clock device that receives start/stop control and a time-up signal generation/-1-cycle 1-1 command from any one of the UI processors, and sends out a clock signal at the specified constant cycle; A multiprocessor system characterized in that it is configured to start a program cycle in each of the above-mentioned block diagrams each time an I-note tie J up signal is input manually.