[go: up one dir, main page]

JPS60147129A - Manufacture of dielectric insulated and isolated substrate - Google Patents

Manufacture of dielectric insulated and isolated substrate

Info

Publication number
JPS60147129A
JPS60147129A JP375184A JP375184A JPS60147129A JP S60147129 A JPS60147129 A JP S60147129A JP 375184 A JP375184 A JP 375184A JP 375184 A JP375184 A JP 375184A JP S60147129 A JPS60147129 A JP S60147129A
Authority
JP
Japan
Prior art keywords
film
etching
etching mask
single crystal
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP375184A
Other languages
Japanese (ja)
Inventor
Tokuo Takeuchi
竹内 徳夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP375184A priority Critical patent/JPS60147129A/en
Publication of JPS60147129A publication Critical patent/JPS60147129A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To produce the titled dielectric insulated and islated substrate with island type single crystal regions subject to different depth and high precision by a method wherein the first etching mask film and the second etching mask film made of different material are laminated to be utilized as successive etching mask for etching operation. CONSTITUTION:The first etching mask film 11 is formed on a single crystal silicon substrate 1 to make openings. The second etching mask film 12 is formed by means of photoetching process so that the film 12 may be composed of a coated part to produce the second shallow etching surface with openings corresponding to the first film 11 and specified depth. Then the substrate 1 is etched to provide the openings with specified depth. Next the second film 12 is removed utilizing acid without doing damage to the first film 11. Then anisotropic etching process is repeated. Later after removing the first etching mask 11, a dielectric film 7 is formed to be coated with polycrystalline silicon 8 as a supporter. Thus island type single crystal regions with different depth may be produced by means of parallel grinding operation.

Description

【発明の詳細な説明】 イ、産業上の利用分野 本発明は半導体集積回路に関し、特に高耐圧を、要求さ
れるような半導体集積回路に用いられる訃。
DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to semiconductor integrated circuits, and particularly to semiconductor integrated circuits that require high breakdown voltage.

電体絶縁分離基板の製造方法に関する。The present invention relates to a method for manufacturing an electrically insulated separation substrate.

口、従来技術 従来、この種の誘電体分離基板は、全て同じ深さに作ら
れた島状単結晶シリコン領堀を支持体中に有する構造で
あるため、半導体集積回路に含まれる低耐圧素子が、高
耐圧素子と同一の大きさの島状単結晶シリコン鎖板に作
られるため、素子寸法の増大など、製造する上で高価力
ものとなる欠点4m才らために、深い島状単結晶シリコ
ン領域と、比較的浅い島状単結晶シリコン領域とを同一
基板内に作ることが考えられてい・る。すなわち、第1
図(a)ないしくe)は、このような半導体装置の製遣
方法を示す断面図でおる。まず第1図(a)のように、
単結晶シリコン基板1にエツチングマスク膜2を形成し
、同図の)のように、エツチングにより幅広の溝3を形
成し、つぎに同図(C)のように溝3の底面に新しいマ
スク膜4を形成し、エツチングによシ、溝5および6を
形成する。それから、第1図(d)のように、溝5,6
の形成された基板面を誘粛5体膜7で覆った後、多結晶
シリコン8を堆積し、つぎに単結晶基板1および多結晶
シリコン80表面を研磨することによシ、同図(e)の
ような、多結晶シリコン8の支持体で支持され、誘電体
膜7によυ互いに島状に分離された、浅い島状単結晶シ
リコン領域9,9および深い島状領域10とを有する誘
電体絶縁分離基板が製造される3゜しかし、このような
従来の方法では、目金せずれなどによる歩留まシの低下
と複雑化している工程のため、高価格となる欠点があっ
た。
Conventionally, this type of dielectric isolation substrate has a structure in which the supporting body has island-like single crystal silicon regions all made at the same depth, so that low breakdown voltage elements included in semiconductor integrated circuits However, since it is made in an island-shaped single crystal silicon chain plate with the same size as the high voltage element, the device size increases and the manufacturing cost becomes expensive. It has been considered to create a silicon region and a relatively shallow island-like single crystal silicon region within the same substrate. That is, the first
Figures (a) to (e) are cross-sectional views showing a method for manufacturing such a semiconductor device. First, as shown in Figure 1(a),
An etching mask film 2 is formed on a single crystal silicon substrate 1, a wide groove 3 is formed by etching as shown in () in the same figure, and a new mask film is then deposited on the bottom of the groove 3 as shown in (C) in the same figure. 4, and grooves 5 and 6 are formed by etching. Then, as shown in FIG. 1(d), the grooves 5 and 6 are
After covering the surface of the substrate on which is formed is an inhibiting five-layer film 7, polycrystalline silicon 8 is deposited, and then the surfaces of the single crystal substrate 1 and polycrystalline silicon 80 are polished. ), which is supported by a support of polycrystalline silicon 8 and has shallow island-like single-crystal silicon regions 9, 9 and deep island-like regions 10, which are separated into islands by a dielectric film 7. However, this conventional method has the drawbacks of lower yields due to misalignment of the metal fittings, and higher costs due to the complicated process. .

ノ1 発明の目的 本発明は、高精度の深い島状単結晶シリコン領域と浅い
島状単結晶シリコン領域とを備えた誘電。
No. 1 Object of the Invention The present invention provides a dielectric comprising a highly precise deep island-like single crystal silicon region and a shallow island-like single crystal silicon region.

俸給縁分離基板を容易かつ安価に製造することを目的と
している。
The purpose is to easily and inexpensively manufacture a salary edge separation board.

二0発明の構成 本発明によれば、単結晶シリコン基板の上に第1のエツ
チングマスク膜と、この第1のマスク膜の浅いエツチン
グ面のための広い開口を塞ぎ、残シの深い溝の為の開口
を合せた第2のエツチングマスク膜を第1のエツチング
マスク族の上に重ねて形成し、第2のマスク膜をマスク
として前記シリコン基板をエツチングした後、前記第2
のエツチングマスク膜を除去し、残った第1のエツチン
グマスク族をマスクとしてエツチングを行い、さらにこ
のエツチングした後のシリコン基板表面に誘電体膜を形
成し、その上に支持体の多結晶シリコンを堆積させ、そ
れから研磨することを含む誘電体絶縁分離基板の製造方
法が得られる。
20 Structure of the Invention According to the present invention, a first etching mask film is formed on a single-crystal silicon substrate, and a wide opening for a shallow etching surface of the first mask film is closed, and a deep groove left behind is removed. A second etching mask film with matching openings for etching is formed over the first etching mask group, and after etching the silicon substrate using the second mask film as a mask,
The etching mask film is removed, etching is performed using the remaining first etching mask group as a mask, a dielectric film is formed on the surface of the silicon substrate after this etching, and a polycrystalline silicon support is formed on the dielectric film. A method of manufacturing a dielectric isolation isolation substrate is provided that includes depositing and then polishing.

ホ・ 実施例 2 つぎに本発明を実施例によシ説明する。E. Example 2 Next, the present invention will be explained using examples.

第2図(a)〜(匂は本発明の一実施例を説明するため
の工程順の断面図である。第2図(a)のように、単結
晶シリコン上に、第1のエツチングマスク膜11を形成
し、半導体集積回路の製造方法として一般に知られる写
真食刻法を用いて開口部を作る。
FIGS. 2(a) to 2(a) are cross-sectional views in the order of steps for explaining one embodiment of the present invention. As shown in FIG. 2(a), a first etching mask is formed on single crystal silicon. A film 11 is formed, and an opening is formed using photolithography, which is generally known as a method for manufacturing semiconductor integrated circuits.

単結晶シリコン1に深い溝を得るようなエツチングにお
いては、エツチング剤として単結晶シリコンの結晶面に
よる異方性を石川しfCKOI(水溶液がよく用いられ
る。KOH水溶液のごときエツチング剤に対しては、第
1のエツチングマスク膜11は単結晶シリコン1を熱酸
化して得られる膜を用いてもよく、写真食刻による開口
部の作製には一般に知られたフッ酸水溶液を用いること
ができる。
In etching to obtain deep grooves in single-crystal silicon 1, Ishikawa uses the anisotropy due to the crystal plane of single-crystal silicon as an etching agent, and fCKOI (an aqueous solution is often used. The first etching mask film 11 may be a film obtained by thermally oxidizing the single crystal silicon 1, and a commonly known hydrofluoric acid aqueous solution may be used to create the openings by photoetching.

次に第1のエツチングマスク膜11の上に第2のエツチ
ング族12を形成する。この第2のマスク膜としては、
例えば、ニッケル、クロム等のよく知られた金属の膜を
用いることができる。クロムのごとき金属を用いれは、
開口部を作製するための写真食刻においては硝酸など酸
によるエツチング可能であシ、多くの酸はシリコンおよ
びシリコンの酸化物をほとんど侵さず、かつクロムの膜
はKOH水溶液に十分カ耐性を有する。第2のエツチン
グマスク族12を、第1のエツチングマスク膜11と一
致する開口部、および所望の深さに第2の浅いエツチン
グ面を得るための被覆部とからなるよう写p食刻法にて
作る。しがる後、&2iI(b)のように、単結晶シリ
コンlの露出部にKOI(水溶液を1例とするエツチン
グを行い、Pfr定の深さにする。所定のエツチング深
さは完成された基板の浅いエツチング面の深さによって
層高される。
Next, a second etching group 12 is formed on the first etching mask film 11. As this second mask film,
For example, a well-known metal film such as nickel or chromium can be used. Using metals such as chromium,
In photo-etching to create openings, it is possible to etch with acids such as nitric acid; most acids hardly attack silicon and silicon oxides, and chromium films are sufficiently resistant to KOH aqueous solutions. . The second etching mask family 12 is photo-etched to consist of openings coinciding with the first etching mask membrane 11 and a covering to obtain a second shallow etched surface at the desired depth. Make it. After etching, as shown in &2iI(b), KOI (for example, an aqueous solution) is etched on the exposed portion of the single crystal silicon l to a predetermined depth of Pfr.The predetermined etching depth is completed. The layer height is determined by the depth of the shallow etched surface of the substrate.

次に、第2のエツチングマスク膜12を前述の酸を用い
、第1のエツチングマスク膜11を抄なわず除去するこ
とにょシ、第2図(C)の断面構造が得られる。単結晶
シリコン1に対し再び異方性エツチングによるエツチン
グ可能を実施すれ//i第2刷(d)に示す構造と外る
。しかる後、第1のエツチングマスク膜11を除去し、
さらに半導体集積回路に用いる誘電体絶縁分離基板と成
すためには、第2図(e)の誘電体膜7を付与した上に
、支持体としての多結晶シリコン8を付着せしめる。誘
電体膜7は単結晶シリコンlを熱酸化して得られる5i
Oz膜であっても、気相成長法などにより付着された膜
であってもよい。第2図(f)に示す構造に成すため、
単結晶シリコン1および多結晶シリコン8をそれぞれの
面よシ平行に研磨することによシ本発明の目的とする深
さの異なる島状単結晶領域が支持体中に埋め込まれた誘
電体絶縁分離基板を容易に得る事ができる。この種の誘
電体膜・縁分離基板を用いて高耐圧素子を含む半導体集
積回路を実現する場合、第2図1(f)に示す単結晶シ
リコン1と同一の導霜型の高濃度層13を設ける事か肩
利であるが、第2図(d)の第1のエツチングマスク膜
11を除去した後に、一般に用いられる拡散方法によシ
容易に形成することか可能である。
Next, the second etching mask film 12 is removed using the aforementioned acid without removing the first etching mask film 11, thereby obtaining the cross-sectional structure shown in FIG. 2(C). When the monocrystalline silicon 1 is etched again by anisotropic etching, the structure differs from that shown in the second printing (d). After that, the first etching mask film 11 is removed,
Further, in order to form a dielectric insulating isolation substrate for use in a semiconductor integrated circuit, polycrystalline silicon 8 as a support is attached on top of the dielectric film 7 shown in FIG. 2(e). The dielectric film 7 is 5i obtained by thermally oxidizing single crystal silicon l.
It may be an Oz film or a film deposited by vapor phase growth or the like. To achieve the structure shown in Figure 2(f),
By polishing the monocrystalline silicon 1 and the polycrystalline silicon 8 parallel to each other, a dielectric insulation isolation structure in which island-shaped single crystal regions with different depths are embedded in the support, which is the object of the present invention, can be obtained. Substrates can be easily obtained. When realizing a semiconductor integrated circuit including a high breakdown voltage element using this type of dielectric film/edge separation substrate, a frost-conducting high concentration layer 13 identical to the single crystal silicon 1 shown in FIG. However, it is possible to easily form it by a commonly used diffusion method after removing the first etching mask film 11 shown in FIG. 2(d).

へ0発明の効果 上述のとおシ、本発明では、第1のエツチングマスク膜
と、この第1のエツチングマスク膜と異なる材料の第2
のエツチングマスク膜とを重ね合せ、ti次エツチング
マスクとしてエツチングを行うことによシ、深さの異な
る高精度の島状単結晶シリコン領域を備えた誘電体絶縁
分離基板を安価に製造できる。
Effects of the Invention As described above, in the present invention, a first etching mask film and a second etching mask film made of a material different from that of the first etching mask film are used.
By overlapping these etching mask films and performing etching as a ti-th etching mask, it is possible to manufacture at low cost a dielectric insulating isolated substrate having highly precise island-shaped single crystal silicon regions having different depths.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(e)は従来の誘電体絶縁分離基板の製
造方法は説明するための工程順の断面図、第2図(a)
〜(f)は本発明の一実施例の製造工程順の断面図であ
る。 1・・・・・・単結晶シリコン基板、2,4・・・・・
・エツチング用マスク、3・・・・・・広い開口、5・
・・・・・浅い溝、6・・・・・・深い溝、7・・・・
・・誘電体膜、8・・・・−・多結晶シリコン、9・・
・・・・浅い島状単結晶シリコン領域、10・・・・・
・深い島状単結晶シリコン領域、11・・・・・・第1
のエツチングマスク膜、12・・・・・・第2のエツチ
ングマスク膜、13・・・・・・高濃度拡散惹。
Figures 1 (a) to (e) are cross-sectional views of the process order for explaining the conventional method of manufacturing a dielectric insulation isolation substrate, and Figure 2 (a)
-(f) are cross-sectional views in the order of manufacturing steps of an embodiment of the present invention. 1... Single crystal silicon substrate, 2, 4...
・Etching mask, 3... Wide opening, 5.
...Shallow groove, 6...Deep groove, 7...
・・Dielectric film, 8・・・・−・Polycrystalline silicon, 9・・
...Shallow island-like single crystal silicon region, 10...
・Deep island-like single crystal silicon region, 11...1st
etching mask film, 12... second etching mask film, 13... high concentration diffusion attraction.

Claims (1)

【特許請求の範囲】[Claims] 単結晶シリコン基板の表面を所望の形にエツチングした
後、この表面を誘電体膜で覆い、さらに支持体物質を堆
積させ、この支持体物質の層で支持され前記誘電体膜で
島状に互いに分離された素子形成の多数の島領域を有す
る誘電体絶縁分離基板の製造方法において、前記単結晶
基板の表面に深い溝と浅いエツチング面を得るための開
口を有する第1のエツチングマスク膜を形成する工程”
と、前記第1のエツチングマスク膜の上に、このマスク
膜の前記探い溝のための開口を合せ、前記浅いエツチン
グ面のための開口を塞いだM2のエツチングマスク族を
形成する工程と、前記第2のエツチングマスク族l:て
前記単結晶基板をエツチングした後この第2のマスク膜
を除去し、残った第1のマスク膜をマスクとして引続き
エツチングする工程とを含むことを特徴とする誘電体絶
縁分前1L基板の製造方法。
After etching the surface of the single-crystal silicon substrate into a desired shape, the surface is covered with a dielectric film, and a support material is further deposited so that islands of the dielectric film are mutually supported by the layer of support material. In a method of manufacturing a dielectric insulating isolated substrate having a large number of island regions for forming isolated elements, a first etching mask film having a deep groove and an opening for obtaining a shallow etched surface is formed on the surface of the single crystal substrate. “The process of
and forming an M2 etching mask group on the first etching mask film, which aligns the opening of the mask film for the search groove and closes the opening for the shallow etching surface; Second etching mask group 1: After etching the single crystal substrate, the second mask film is removed, and etching is continued using the remaining first mask film as a mask. A method for manufacturing a 1L dielectric insulation board.
JP375184A 1984-01-12 1984-01-12 Manufacture of dielectric insulated and isolated substrate Pending JPS60147129A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP375184A JPS60147129A (en) 1984-01-12 1984-01-12 Manufacture of dielectric insulated and isolated substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP375184A JPS60147129A (en) 1984-01-12 1984-01-12 Manufacture of dielectric insulated and isolated substrate

Publications (1)

Publication Number Publication Date
JPS60147129A true JPS60147129A (en) 1985-08-03

Family

ID=11565893

Family Applications (1)

Application Number Title Priority Date Filing Date
JP375184A Pending JPS60147129A (en) 1984-01-12 1984-01-12 Manufacture of dielectric insulated and isolated substrate

Country Status (1)

Country Link
JP (1) JPS60147129A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03245552A (en) * 1990-02-23 1991-11-01 Matsushita Electric Works Ltd Manufacture of insulating layer isolated board material
US6664032B2 (en) * 1999-02-16 2003-12-16 Canon Kabushiki Kaisha Method of producing two-dimensional phase type optical element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03245552A (en) * 1990-02-23 1991-11-01 Matsushita Electric Works Ltd Manufacture of insulating layer isolated board material
US6664032B2 (en) * 1999-02-16 2003-12-16 Canon Kabushiki Kaisha Method of producing two-dimensional phase type optical element

Similar Documents

Publication Publication Date Title
JPH01315159A (en) Dielectric-isolation semiconductor substrate and its manufacture
US3844858A (en) Process for controlling the thickness of a thin layer of semiconductor material and semiconductor substrate
JPS6362897B2 (en)
US3969749A (en) Substrate for dielectric isolated integrated circuit with V-etched depth grooves for lapping guide
JPS60147129A (en) Manufacture of dielectric insulated and isolated substrate
JPH0488657A (en) Semiconductor device and manufacture thereof
JPH03105944A (en) Method for manufacturing dielectric isolation substrate
JPS5828731B2 (en) All silicon materials available.
JPS60167439A (en) Manufacture of complementary dielectric isolation substrate
JPH0230177A (en) Semiconductor device
JPS6387762A (en) Manufacture of semiconductor device
JPS6359531B2 (en)
JPS58197740A (en) Manufacture of substrate for integrated circuit
JPS5455181A (en) Production of semiconductor substrate
JPS6244415B2 (en)
JPH02260442A (en) Dielectric isolation type semiconductor substrate
JPS63213932A (en) Manufacture of complementary dielectric isolation substrate
JPS6359532B2 (en)
JPS6298639A (en) Manufacture of dielectric isolated substrate
JPS6288334A (en) Manufacture of dielectric insulation isolating substrate
JPS63221637A (en) Complete dielectric isolation structure in silicon wafer and manufacture of its structure
JPS61287142A (en) Manufacture of dielectric isolated substrate
JPH0117246B2 (en)
JPH03295255A (en) Manufacture of insulating layer isolating substrate
JPS59215746A (en) Manufacture of semiconductor device