JPS60146521A - Voltage comparison circuit - Google Patents

Abstract

PURPOSE:To decrease an offset voltage and to avoid fluctuation by matching a threshold voltage of an inverter of the next stage with voltage in the steepest voltage range of an output inverting characteristic of a comparator section in a C-MIS voltage comparator circuit. CONSTITUTION:A gate of an N-MISFET26 is connected to the 1st input terminal 29 and a gate of a P-MISFET25 is biased by an output voltage of comparator sections 21, 22, 23, 24, then the inverting threshold value of the inverter of the next stage comprising FETs 25, 26 is coincident with the voltage changing most steeply in the inverting characteristic of the comparator sections at all times. That is, the inverted threshold voltage of the inverter of the next stage is changed as an input voltage changes and the operating point of the inverter is moved to the optimum operating point, then no mismatching is caused, the offset is not fluctuated over a wide input voltage and the offset is constituted in a small value.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary M field effect transistor (hereinafter referred to as 0
-Abbreviated as M-5FET. ), and relates to a voltage comparison circuit that prevents IE of off-cent voltage due to input voltage fluctuation.

As a conventional example, an example of a voltage comparison circuit constituted by a C-M 5FET is shown in FIGS. 1(a)' and 1(b). 1st
The diagram (a) is divided into a voltage comparator section made up of MISFETs 1 to 4, and an inverter section made up of M5FETs 6 and 7. A voltage vl is input to the input voltage terminal 10, and a voltage v2 of the other input terminal 1'1.12 is input. The value of one input voltage V, vI (')9V, (2
), V, (3) K versus the other input voltage v2
When variable, the output inversion characteristic of the voltage comparator is
As shown in the figure. The value of input voltage v1 is V, (11-)V
l (21→Vl(3)), the voltage width of the steep part of the output inversion voltage v out narrows.Accordingly, the threshold voltage V of the next stage inverter
Threshold voltage VT when THI is optimally designed
When the value of HI is f VT'HI (1) and the value of input voltage v1 is Vl(3), the value of threshold voltage VTHI when a mismatch occurs is VTR(2).

For VTHI (2), the offset voltage is v 2 =
It suddenly increases at v 1 (s), causing circuit malfunction.

Conventional circuits using ordinary CM S inverters in the amplification stage have the disadvantage that mismatches are likely to occur depending on the temperature characteristics of the circuit and the input voltage. In addition, Fig. 1 (a
), the voltage comparison section is a P-channel M5FETI, 2
and N-channel M-type 5FET6.4, and the output inverter section is composed of P-channel M-type 5FFiT6 and N
It is composed of a MISF FiT7. Power terminal 1
5.14, input terminals 10 and 11, and output terminal 12. FIG. 1(b) shows a voltage comparator circuit driven by a constant current, which includes a constant voltage circuit 15 and an M-type 5FET 5i for constant current control.

The present invention has been made to eliminate the above-mentioned drawbacks, and provides a C-M S voltage comparator circuit that is easy to design, has a wide input voltage range, and has a low offset voltage.

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 5 shows a circuit diagram of a first embodiment of the present invention.

The output voltage terminal 52 of the voltage comparison section is connected to the gate of the P-channel MISFET 25 of the next stage amplification section, and the gate of the N-channel MISFET 26 is connected to the first input terminal 29. Since the gate of the N-channel MISFET 26 is connected to the first input terminal 29,
The inversion threshold voltage of the next stage inverter consisting of transistors 25 and 26 varies with the first input voltage.

This situation is shown in FIGS. 5 and 6. Figure 5 shows the current-voltage characteristics a and P-channel MI of N-channel M5FET2
The current-voltage characteristics of SFET25 are fully shown. Figure 6 shows the output inversion characteristics of the comparator section consisting of M-EINETs 21, 22, 26 and 24, and the inversion operating point VTR,I (A) of the subsequent inverter consisting of MISFETs 25 and 26.
'I VTHI (B) and VTHI (C) are shown. The gate of M I S y, Bli T 25 is biased by the output voltage of the comparator section,
- The gate of the P-channel MISFET 26 is biased by the voltage at the input 29 of the converter, so the inversion threshold of the second inverter always matches the voltage at which the inversion characteristic of the converter changes most steeply. As shown in the inversion characteristics of the comparator in Figure 6, the threshold voltage for inversion of the subsequent inverter is VTHI (A) with respect to the input voltage value v2.
, VTHI t, B), and VTHI (C). The greatest feature of the present invention is that the inverting operating point of the inverter changes with the input voltage in this way, and the operating point of the inverter moves to the optimal operating point.

The P-type M5FET 25 turns on and off as the output voltage of the voltage comparator 52 changes, so that the threshold voltage of the next-stage inverter always matches the steepest voltage value of the output reversal characteristic of the voltage comparator 62. Since there is no mismatching, there is no offset variation over a wide range of input voltage values, and the offset voltage value is small, the optimum characteristics as a voltage comparison circuit can be obtained. In the first embodiment, P-channel MISFETs 21, 25.25 and N-channel MISFET
'ET22, 24.26, and has an input voltage terminal 29.50 and an output voltage terminal 61.

A second embodiment of the invention is shown in FIG. This Leri is a voltage comparison circuit driven by constant current, and includes a constant voltage circuit 48 and an MIS=1.BT 45 that supplies a constant current to the circuit. N-channel MISFET in the next stage inverter section
46 is the value dedicated to the N-channel) A5FET 45: S F Fi T, and the first current value ■l, the second current value ■2, and the fifth current value ■3 are manufactured equally. This also applies to the embodiment shown in FIG. In addition, in order to keep each current value constant, it is necessary to
The threshold voltages of ET are all equal, and similarly N child M
The threshold voltage of S17'BT must also be set equally.

Further, FIG. 7 shows a fifth embodiment of the present invention.

In the first and second examples, N-channel M S Il'E T
In the third example, the P channel is driven by M5FETi. The voltage comparison section is P
It consists of M-channel 5FET60, 62.64 and N-channel M-5FET61.65.

1. % E inverter section is P channel M engineering sFg'r6
It consists of 5°67 and N channel 1i 5FET6/l.

In addition, the constant voltage circuit that supplies the constant voltage P-channel M-5FET is connected to the P-channel M-5NET69 and the N-channel M-5FET.
It is made with FET68. Other input voltage terminals 70.7
1 and power supply terminals 75 and 72.

As described in detail above, according to the CM S voltage comparator circuit of the present invention, the threshold value of the next stage inverter is always matched with the input voltage within the steepest voltage range of the output reversal characteristic of the voltage comparator section. It is an object of the present invention to provide a voltage comparator circuit that is easy to design and useful, in which there is no variation in off-cent voltage due to voltage variation, and in which the off-cent voltage is kept low.

[Brief explanation of the drawing]

1(a) and 1(R(1)) are circuit diagrams of a conventional voltage comparator circuit, and FIG. 2 is a graph showing the output inversion characteristics of a conventional voltage ratio circuit. FIG. 5 is a circuit diagram of the first embodiment of the voltage comparison circuit according to the present invention, FIG. 4 is a circuit diagram of the second embodiment of the voltage comparison circuit of the present invention, and FIG. 5 is the current of the final stage inverter of the present invention. FIG. 6 is a graph showing voltage characteristics; FIG. 6 is a graph showing the inversion threshold voltage of the final stage inverter of the present invention; FIG. 7 is a circuit diagram showing a fifth embodiment of the present invention. 21, 23・ii Pressure comparison section P-channel MISFET. 22.24... Voltage comparison section N-channel M, TSFET
. 25...Inverter section P channel M engineering 5FET. 26...Inverter section N channel M engineering 5FET129
．． 50... Input voltage terminal, 51... Output voltage terminal, 27... VOO terminal, 28... VSS terminal. a) Figure 1 (b) Figure 2 2 Figure 3 11/Jθ Figure 4 j Figure 5 OVsρ Figure 6 2 Figure 7

Claims (1)

[Claims] (1) A circuit in which the drain of a first MIS field effect transistor of a first conductivity type and the drain of a second MIS field effect transistor of a second conductivity type are connected in series;
a circuit in which the drain of a fifth M field effect transistor of conductivity type and the drain of a fourth M field effect transistor of second conductivity type are connected in series;
A circuit in which the drain of the MIS field effect transistor and the drain of the sixth MIS field effect transistor of the second conductivity type are connected in series is connected in parallel to the power supply,
Connecting the connection point of the first and 82nd MXB field effect transistors to the gate electrodes of the first and sixth MXB field effect transistors, and connecting the third and fourth MISt field effect transistors. A voltage comparison circuit characterized in that the point and the gate electrode of the fifth field effect transistor are connected, and the gates of the second and sixth field effect transistors are connected.