JPS6014366A - Daisy chain circuit - Google Patents

Abstract

PURPOSE:To secure the normal actuation of a daisy chain circuit with no cut-off of the daisy chain despite the removed of undesired devices set on a mother board, by providing an internal logical circuit consisting of plural AND means in order to increase the number of wirings. CONSTITUTION:The 2nd device 20 is taken out of a mother board, and an interruption request signal IREQ is delivered from the 3rd device 30. In such a case, a terminal j3 of the device 30 is set at a high level by a pull-up resistance. If a CPU1 permits an interruption of the device 30, a signal IACK0 is supplied to a terminal j1. Thus the terminal j1 is set at a high level. While the 1st device 10 delivers no interruption request and therefore delivers a signal of a high level via a terminal (k) by the pull-up resistance. Therefore a terminal j2 of the device 30 is also set at a high level, and it is confirmed that the CPU1 has permitted an interruption. Thus a normal function is maintained for a daisy chain circuit without changing the layout of devices and the forms of wirings and even after the device 20 is taken out of the mother board.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a deci-chain circuit in which a mother connects a plurality of devices on a board with appropriate priority.

[Prior art]

FIG. 1 shows a case where the conventional deci-chain method is applied to an interrupt circuit.

In FIG. 1, the CPUI, the first device IO, the second device 20, etc. are installed on the same motherboard, and the peripheral devices such as the first device 10, the second device 20, etc. are connected to the CPU 1. All are commonly connected by the same interrupt request line IREQ. When any peripheral device sends an interrupt request signal to the CPUI via the interrupt request line I REQ, the CPU 1 receives the interrupt request signal, and if it is OK to accept the request, sends an interrupt via the interrupt acknowledgment line IACK. Sends back a permission signal. As shown in FIG. 1, the return is first input to the first device IO, then the 27th'' pie 20, etc., and so on. Therefore, each peripheral device], 0, 20... must be provided with internal logic for transmitting the above-mentioned interrupt acknowledgement except for the last device, which cannot transmit the AiJ interrupt acknowledgement anywhere, and this internal logic must be provided in the second device. This internal logic consists of an AND gate 5, one input of which is connected to the irritable response line LACK via terminal 1!, and the other input terminal is connected to the interrupt + A mask signal MA having the opposite logic to the request signal is input.

In other words, the mask signal MA is 1lliiiI when the device in question is sending an interrupt request signal to the CPU I.
It is implicitly set to "0", and if the relevant device does not issue an interrupt request signal to CPU 1, the logical value is "0".
1". The AND output of the AND dart 5 is sent to the 1 of the next device via the terminal 12 of the device.
Input to one terminal. Therefore, for example, if the 17'th device 10 does not send an interrupt request signal to the interrupt request line I REQ, the mask signal MA has a logic value of "l".
The interrupt permission signal sent from the CPU 1 is transmitted to all the second devices 20, but if the 17th device 10 is sending a non-interrupt request signal to the CPU 1, the mask signal MA described in 2. has a logic value of "0" and transmits the interrupt enable signal sent from CPU 1 to the next second device 20.
Thereafter, the first device 10, which has recognized the interrupt permission, sends an address vector to the CPU 1 via a data bus or the like. That is, in this case, the 17'th device 10 is given the highest interrupt priority, and then the 27'th device 20, the third device 30, etc. have lower interrupt priorities.

In this way, in the conventional easy chain system, priority is determined by the position of each device on the pine board or the manner in which it is connected. Therefore, if a device on the motherboard is no longer needed in the system configuration (
For example, in a system that does not handle analog signals,
(no digital or digital-to-analog conversion device is required), simply removing the device
The dc chain is interrupted in the middle, and normal functionality is no longer realized. Therefore, in the conventional method, in such a case, the remaining board must be re-inserted without breaking the DIN chain, or the wiring or DIN
I have done this and have addressed the above. Also, depending on the purpose of use, such as a personal computer system, etc.
If one required device is different, the insertion position of the device may be different depending on each user, and in this case, it is necessary to perform the same process as above. This requires a lot of labor and time when a large number of substrates need to be processed, for example during manufacturing, shipping, or repair.

[Purpose of the invention]

This invention was made in view of the above circumstances, and provides a decimal chain circuit that can operate normally without breaking the decimal chain even if unnecessary devices on the motherboard and +p- boards are removed. The purpose is to provide.

[Structure of the invention]

Therefore, in the present invention, a main device (for example, a CPU in an interrupt circuit) and a subordinate device (for example, a peripheral device in an interrupt circuit) that are subordinate to the main device are fixedly arranged at predetermined positions on a motherboard. fit L
, the response signal of the main device in response to a p91-specific request of the slave device further comprising internal logic circuits of all the slave devices (whether or not the response signal from the master device is propagated to a subordinate device with a lower priority than the slave device) For all dependent devices, the output of the internal logic circuit of the dependent device is commonly connected to one input terminal of the circuit that controls the dependent device, and the output of the internal logic circuit of the dependent device is also commonly connected to all dependent devices that have a lower priority than the dependent device. At the same time, the internal logic circuits of all dependent devices are provided with pull-up means for forcing the input signal to an active level when the input of the internal logic circuit is open. The internal logic circuit includes a first AND means for ANDing all input signals, and an output of the first AND means and an output from the main device to the slave device having a lower priority. and a second logical product means whose logical product (6) is an output signal to a subordinate device having a lower priority than the dependent device. Consists of.

〔Example〕

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The decimal chain circuit according to the present invention will be described in detail below with reference to embodiments shown in the accompanying drawings.

FIG. 3 shows an embodiment of the decimal chain circuit according to the present invention applied to an interrupt circuit.

In FIG. 3, a CPU 1, a first device 10, a second device 20, a third device... are mounted on the same motherboard, a first device 1o, a second device 20... This is the same as the conventional method described above in that all of the peripheral devices are commonly connected to the CPU 1 by the same interrupt request line IREQ, but in this case, the CPU 1
interrupt acknowledge signal IACKO! The propagation method of .

The interrupt acknowledgment P number IACKO of the CPU] is commonly connected to the j+ input terminal of all peripheral devices.

01 of the first device 10 for the signal IACKQ
The output IACKl of the internal logic j is sent to all peripheral devices 20, 30, . . . which have a lower priority than the first device 10.
・Commonly connected to the j2 input terminal of . Similarly below,
Peripheral device 8-Dibθ bond cleaning process 4-
The output of the internal logic of 3-4 is IACK 2 , IAC
K3... are commonly connected to predetermined input terminals (j3...) of all peripheral devices having a lower priority than the peripheral device.

Next, the circuit configuration of the internal logic provided in each peripheral device is shown in FIG. 4, and this circuit particularly corresponds to the internal logic of the third device 30.

In FIG. 4, this internal logic consists of an AND gate 7 and a sol-up resistor r connected to each input line of the AND gate 6. The input terminals of Ampique 9-Toro are the aforementioned LACK O and I via terminals j+ and j2yjak.
The ACK 1 and IACK 2 signals are input, and their AND output is connected to one input terminal of the AND dart 7. In addition, the other input terminal of ANDDART 7 receives an interrupt request signal I REQ as described in 1111.
A mask signal MA having the opposite logic is input. By the way, according to this circuit, since the pull-up resistor r to which the P9i constant voltage V is applied is connected to the input of the AND gate 6, for example, it is not connected to the terminal j1 or any output and is in an open state. Even if it is terminal j! The input terminal of the AND gate 6 corresponding to the logic level should not be at a high level, and the output of the AND gate 6 would not be adversely affected.
And date 6 is the other input IACK 1, IACK
It will output a logical output based on 2. Of course the fourth
The logic shown in the figure directly corresponds to the 37th J device 30, but other peripheral devices also have similar internal logic, and the difference is simply in the number of input signals. be.

Next, the operation of the embodiment apparatus shown in FIGS. 3 and 4 will be explained in three cases.

(1) All peripheral devices are inserted on the motherboard (9
), and the interrupt request signal 1REQ is output from the first device 10; In this case, the internal logic in the 17'' device 10 is such that the j2 and j3 terminals of the configuration shown in FIG. It corresponds to the open state that is not connected.CP
If U1 allows interrupts, the IA
Since the CKOQ signal is input at a logical high level and the terminal j2*js is at a high level due to the sol-up resistor r, the output of the Ampique 9-Toro is at a high level. Accordingly, the first device 10 recognizes that the CPU 1 has permitted the interrupt. It's a trench, 1st device 1
Since 0 is sending the interrupt request signal IREQ, the mask (m MA) becomes low level at the logic level, and the output IACK 1 of the AND gate also becomes low level.Therefore, the peripheral devices after this lever include the CPU, The interrupt enable signal of 1 is not propagated.Of course, if the CPU 1 does not permit interrupts, the interrupt acknowledge line TACKO remains at low 1/bell, and the first device 1o recognizes this.

(2) Is the second device 20 the mother day? - Sampling (1)
0) and the interrupt request signal IREQ is output from the third device; In this case, since the second device 20 does not exist, the terminal j3 of the third device 30 is in an open state, but it is set to a high level by the sol-up resistor. It becomes. CPU
1 allows interrupts of the third device 30, the third device
The IACK Q signal is input to the terminal j1 of the device 30, and this terminal, I+, becomes high level. In addition, since the first device 10 has not issued an interrupt request, the mask signal MA in the 17' device 10 is at a high level, and the output of the AND/DART 6 in the first device 10 is also at a high level due to the sol-up resistor r. to become the first device 1
The output of the AND/DART 7 within 0 is at a high level, and this is outputted via the terminal k. Therefore, the terminal j2 of the third device 30 also becomes high level. As a result, the output of the AND gate 6 of the third device 30 becomes high level, and the third device 30 recognizes that the CPUI has permitted the interrupt. Since the mask signal MA of the 37th J device 30 is at a low level for the reason described above, the interrupt enable signal of the CPU 1 is not propagated to subsequent peripheral devices.

In this way, according to this embodiment, even after the second device is removed, normal operating functions can be maintained without changing the layout or wiring of the device.

(3) When the first device 0 and the second device 20 are removed from the motherboard and the third device 3 outputs the interrupt request signals IRF and Q; in this case, the first device 10 and the second device Since device 20 does not exist, the third
Both terminals j2 and j3 of the device 3o are in an open state, but are at a high level due to the sol-up resistance. In addition, when CPU 1 allows interrupts from third device 3o, TACK is sent to terminal j1 of third device.
Since the Oig signal is input and the terminal j+ also becomes high level,
The output of the AND dart 6 of the third device 30 is at a high level, and the third device 3o recognizes that the CPU 1 has permitted the interrupt. Since the mask signal MA of the third device 30 is at low level, the interrupt enable ID of the CPU 1 is not propagated to the subsequent peripheral devices. As described above, according to this embodiment, even after the first device and the second device are removed, the device remains fixed and the normal disso chain function is maintained without changing the arrangement number or wiring pattern of the device. can be maintained.

In addition, in the fc embodiment shown in FIG. 3, the case where there are three peripheral devices has been explained, but even when more peripheral devices are added, the principle shown in FIGS. 3 and 4 can be used. Of course, the functions of the present invention can be easily achieved by simply increasing the number of wirings on the motherboard and increasing the number of internal logic inputs.

Furthermore, the internal logic for propagating the interrupt acknowledgment signal used in the present invention is not limited to that shown in FIG. Of course it's a good thing.

By the way, in the above-mentioned embodiment, the case where the present invention is applied to (13) interrupt circuit has been explained, but the scope of application of the present invention is not limited to this. For example, many systems use the deci-chain method for direct memory access (DMA) and path arbitration in multi-processor set systems.
By applying the present invention, it is possible to obtain effects similar to those described with respect to the interrupt circuit. In short, the present invention can be applied to any circuit as long as a master device and a plurality of subordinate devices are connected in a predetermined priority order.

〔Effect of the invention〕

As explained above, according to the technological chain circuit according to the present invention, even if unnecessary devices are removed from the motherboard due to changes in the system configuration, etc., the devices can be rearranged or the wiring pattern can be changed. Since the IC chain can be operated normally without any problems, substrate processing with ignition can be carried out easily and with high efficiency.

(14)

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional decimal chain circuit, FIG. 2 is a logic circuit diagram showing a conventional circuit configuration for a decimal chain, and FIG. 3 is a block diagram showing an example of a conventional decimal chain circuit. Block diagram showing one embodiment, No. 4
The figure is a logic circuit diagram showing an example of the circuit configuration of each peripheral device in the embodiment shown in FIG. 3. l...CPU, 5.6.7...and dart, 1
．． 0.20'. 30... Peripheral device, r... Pull back f resistance. Figure 1 Figure 3

Claims (1)

[Claims] In a disoi chain circuit in which a plurality of slave devices subordinate to a master device are connected in cascade according to a required priority order, all outputs from the master device are commonly connected to all of the slave devices. At the same time, the output of each of the dependent devices is also commonly connected to all of the subordinate devices of lower priority, and a first logical product is provided in each of the dependent devices to logically multiply all the input signals. means and said first
a second logical product means for calculating a logical product between the output of the logical product means and a signal for determining whether or not the output from the master device is further propagated to a subordinate device having a lower priority than the slave device; and a sol-up means for forcing the input signal to an active level when the input of the first ANDing means is open, and outputting the output of the second ANDing stage from the slave device. A decimal chain circuit that outputs an output signal to a subordinate device with a low priority.