JPS60140454A - Storage section controller - Google Patents

Abstract

PURPOSE:To attain effective utilization of an access selection circuit and efficient access processing by dividing the access selection circuit into the own system and the other system use and applying access selection after the address conversion in the said circuit so as to eliminate useless access selection. CONSTITUTION:An address converting circuit ADCNV(0, 1) is placed before the address selection circuit S(0, 1) and the address selection circuits are provided as S(0, 1) for the own system memory storage device MSU(0-3) and an RS(0, 1) of other system MSU. An access from a CPU0 is set to a port P1' of an MCU0 and converted into an address by the ADCNV0. The access applied with the address conversion is set to a port P1 and inputted to the own system address selection circuit S0 or the other system address selection circuit RS0 and selected. The access is subject to address conversion and fed to the own system or the other system address selection circuit while whether the address is for the own system or the other system is recognized, and selected according to the priority level.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a storage controller that controls access to a main memory, and more particularly to a plurality of storage controllers that mutually transmit data.

Prior Art and Problems As shown in FIG. 1, there are a plurality of storage controllers MCU, two in this example, MCUO and MCUI, and each of the storage controllers has a plurality of access generators (central processing units) C.
PUO and CPUI, CPU2 and CPU3, main storage MSUO and MSUI, MSU2 and MSU3 are connected,
A complex system is considered in which the MCUO and MCU1 are interconnected and can transmit data. In such a complex system, the CPU and MSU are connected only to each MCU (does not have an interface), so the CPU and MSU are connected only to their own system (MCU and the CPUs connected to it).

Access within MSU is as usual, but access across other systems is CPU - own system MCU = other system MCU - that M
The route S'U will be taken. For example, when CPU0 accesses MSU2, the access
The MS is transmitted via the route MCUO-MCUI-MSU2.
U2 is activated, and if the access is a read request, the read data is transmitted to CPU0 via the reverse route. In the case of self-system access, for example, when CPU2 accesses MSU3, the access generated by CPU2 (also referred to as a fetch request) is passed to MCUI, and MCUI passes it to MSU3, where MSU3 starts and reads it. Upload the data to MCUI, MCUI sends it to CPU2
The procedure is to pass it on to.

In this way, the MCU in a complex system receives accesses from its own system and other systems, and since there are multiple CPUs in its own system, accesses from each of them enter, and these are prioritized and MSU
It must be selected based on the busy state of the MS, etc., and handed over to the corresponding MS or U. When considered simply, this access selection process is as shown in FIG. 2.

In Figure 2, P is a register called a port, S and R
3 is a selector, ADCNV is an address converter, and subscripts o, i, . . . are used to distinguish them from each other.

Other system access For example, when CPU0 accesses MSU2, access acceptance from CPU0 to MCUO is set in register P1, and access selection circuit SO
is selected.

The selected access is converted by a circuit ADCNV that converts the address (real address) into a physical address,
In this example, the address (physical address) after this conversion is MS
Since it shows that it is in U2, Regis'riR
Remote access selection circuit R3O via R7 or R8
is input, and selected here, port P13 of MCUI
sent to.

In MCUI, the access received at port P13 is selected by selection circuit S1, and the address is already converted by address translation circuit ADCNv1, so it simply passes through) and is sent to MSU2 via port P15.

If the access is a feck request, the accessed MSU2 reads the memory and stores the read data in the MSU2.
SU2 is sent to CPU0 via MCUI and MCUO (this route is not shown). The MCU also includes an access vibe line to receive read data from the MSU, but is not shown here.

In the device shown in FIG. 2, the access selection circuit so receives accesses from the CJU of its own system as well as accesses from cPUs of other systems, and selects them based on predetermined selection criteria. Then, real-physical address conversion is performed for the access that should be to the own MSU, and at this stage it is known whether the access is to the own MSU or the other MSU, and if it is the other MSU, it will be sent to the other MCU. .

If an access is to an MSU of another system, the data should be sent to the MCU of the other system before being selected by the selection circuit SO, so the method shown in FIG. 2 is wasteful.

Purpose of the Invention The present invention provides a storage controller MC incorporated in a complex system.
The purpose is to perform access processing in U rationally and to enable efficient access selection.

Composition of the Invention The present invention provides a system in which a plurality of access generation devices and main storage devices are connected to each other, and in a plurality of storage unit control devices that are connected to each other and perform access and data transmission/reception, an access generation device of its own system is generated. An address conversion circuit that converts an access address into a physical address, and an address conversion circuit that converts an access address into a physical address, and an access that is determined to be an access to the main memory of the own system as a result of the address conversion, and an access to the main memory of the own system from another system. For own system to receive and select access −′
The present invention is characterized by comprising an address selection circuit, and an address selection circuit for another system that selects an access that is found to be an access to a main memory of another system as a result of the address conversion. Let me explain this.

Embodiment of the Invention FIG. 4 shows an embodiment of the invention, in which the same parts as in FIG. 2 are given the same reference numerals. As is clear from comparing the two, in the present invention, the address conversion circuit ADCNV is placed before the address selection circuit S.

In addition, the address selection circuit is S for own system MSU and MSU for other system.
It is divided into R3 and that for SU. In the figure, the system is a composite of two systems, but of course it may be a composite of any n (n>1) systems, and in this case, (n-1) selection circuits for other systems (remote access selectors) are provided. If it is dedicated to each system, it can be directly connected to the MCU of each system via a boat P7' or the like.

The address converter ADCNV converts a real address into a physical address, but a physical address is an address that indicates somewhere in the actual memory, and a real address is an address assigned during mapping. However, it is still not at the level of accessing actual memory. To give a specific example, if the main memory MSU is constructed of eight memory chips each having 256 addresses, the size of the address space is 2048. Its 0~255,256~511,512~765°...
... is the first. Second. Third. It may be established in the memory chip of ......, and also O~15.16~31.32
~47. ...... as the first. Second. Third.・・・・・・
128 to 143,1 after one round of memory allocation
44-159, 160-175. . . . again from 1st to 2nd. It is also possible to allocate it to the third memory, and so on. Address 0-204 in this case
7 is a real address, an address on the actual memory chip; in the latter example above, address 16 is the memory address of the first row, first column of the second memory, etc. are physical addresses.

The address translator ADCNV performs this real-to-physical address translation. FIG. 5 shows its internal structure. This consists of registers R1 to RN and selectors Sb and Sc, and the registers R1 to RN are provided in the same number as the memory chips, and each register is made up of a physical address of the memory chip and a valid bit V indicating whether the address is valid or invalid. . CPDo,
Accesses RAO and RA'1 issued by the CPUI enter selectors Sb and Sc, select one of the corresponding registers R1 to RN with the upper bits of the access, and store the physical address PAO therein.

Read PAl. In this example, there are two accesses input to the address converter, RAO and RAI, so the selector is S.
There are two selectors 3b and Sc, but if the number (types) of accesses input to the address converter is large, the number of selectors 3b, Sc, . For example, as shown in Figure 2, the address converter ADCNV
If there is one access input to O, the selector is Sal
That's fine.

The operation in Fig. 4 is performed in the same way as in Fig. 2, where CPU0 is the MSU.
2, the access from CPU0 is set to MCUO's boat PI', and A
The address is converted by DCNVO. This address-converted access is set to boat P1, and since this access indicates not the own system's MSU but the other system's MSU2, it is not input to the own system's address selection circuit SO, but is for other systems (remote system). address) is input to the address selection circuit R3O, selected by this, and sent to the MCUI through the port P7'.
sent to. Access sent to MCUI is from boat P1
3, selected by the address selection circuit S1, and sent to the MSU2 via the boat P15. When receiving an access, MSU2 reads the memory if the access is a data fetch request, and the read data is stored in MSU2.
It is sent to CPU0 via CU1 and MCUO, but this route is not shown.

In the circuit shown in Figure 4, the access is address-converted and sent to the own-system address selection circuit or other-system address selection circuit after determining whether it is for the own system or another system, and is then selected according to the priority level, etc. There are no wasted choices.

In Figure 2, the access is first selected, then the address is converted, and if it is determined that it is for another system, it is sent to the other system, where it is selected again, and so on, so there is a lot of waste and there is a risk that the time required will be large. be. However, in Figure 4, the access input to the MCU is first input to the address converter, so the AD
The number of CNV inputs is large, and the number of selectors S is also large.

In the embodiment, the self-system address selection circuit was common to the two MSUs, but it may be provided in multiple numbers corresponding to each MSU, or if a large number of MSUs are connected to an MCU, they may be divided into groups. An address selection circuit may be provided corresponding to each group.

As described in detail, according to the present invention, the access selection circuit is divided into one for the own system and one for the other system, and access selection is performed after address conversion by these circuits, thereby eliminating unnecessary access selection and reducing access selection. Effective use of circuits and more efficient access processing can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an overview of a complex system to which the present invention is applied, FIG. 2 is a block diagram showing an example of the configuration of a storage controller in the system of FIG. 1, and FIG. 3 is a part of FIG. 2. FIG. 4 is a block diagram showing an embodiment of the present invention, and FIG. 5 is a block diagram showing details of a part of FIG. 4. In the drawing, CPU is an access generation device, MSU is a main storage device, MCU is a storage controller, ADCNV is an address conversion circuit, S is an access selection circuit for the own main storage device,
R3 is an address selection circuit for other systems. Applicant Fujitsu Limited Representative Patent Attorney Minoru Aoyagi

Claims (3)

[Claims] (1) In a plurality of storage control devices each connected to a plurality of access generation devices and main storage devices, which are connected to each other and perform access and data transmission/reception, accesses generated by the access generation device of the own system. an address conversion circuit that converts the address of the system into a physical address; The present invention is characterized by comprising: an address selection circuit for the own system that performs access selection based on the address conversion; and an address selection circuit for the other system that selects an access that is found to be an access to the main memory of the other system as a result of the address conversion. Storage controller. (2) The storage unit control device according to claim 1, wherein the access selection circuit for other systems is provided as many as the number of other systems, and is dedicated to each of the other systems. (3) A plurality of self-system access selection circuits are provided corresponding to individual or groups of main storage devices connected to the storage controller, and are dedicated to each of them. The storage unit control device according to item 1.