JPS60138664A - Data bus system for devices with different required data bus widths - Google Patents

Abstract

PURPOSE:To decrease the number of data bus connection lines among secondary devices having small necessary data bus width to simplify the constitution and to reduce the hardware quantity, by using a data selection control circuit, etc. for switching connection to a main memory area. CONSTITUTION:An arithmetic processor BPU1 having the parallel transfer bit number equal to the double byte width and a selector port S-PORT2 are connected to MSC data buses 10 and 11 respectively. While a multiplexer port M- PORT3 having the transfer bit number equal to the single byte width is connected only to the bus 11. In this case, main memories MS05a and MS15b are connected with switching to the desired areas after receiving the control information via data selecting circuits 40 and 41 within a main memory 4, a data selection control circuit 6, MSC interface control lines 30a-30c, etc. This decreases the number of connection lins to data buses for a secondary device of a port M-PORT, etc. having small necessary data bus width. As a result, the constitution can be simplified with reduction of hardware quantity.

Description

Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to an information processing device in which a main device and a plurality of sub devices exchange data via a data bus, and in particular, to A data processing system in which peripheral devices are configured to access main memory via a data bus is one example in which the present invention may be applied.

[Background of the invention]

Conventionally, a data bus connecting a main device (e.g., main storage device) and various sub-devices (e.g., various peripheral devices) has been used to store data 11 required by the sub-device having the maximum required data bus width.
A sub-device that has @ and requires a small data bus width also has a connection for the full data width of this data bus, and a buffer device is installed on the sub-device side to assemble and assemble data before and after transfer.
It is common to take measures such as decomposing the data or transmitting the same data side by side. As a result, the amount of hardware increases, and for subdevices with a small required data bus width, it is necessary to accept extra data lines, resulting in implementation problems such as having to provide more pins than necessary when converting to an LSI. There are also some difficulties.

One way to reduce the number of required pins is to reduce the data width of the data bus, and for devices with a large required data bus width, divide the data into multiple times, so-called time-division transfer, and then transfer the original data on the receiving side. The first thing to do is to return it to its original width and then process it. However, this method does not only complicate data transfer control, but also reduces data transfer capability (throughput).

[Purpose of the invention]

The purpose of the present invention is to eliminate the drawbacks of the prior art as described above,
For sub-devices that require a small data bus width, reduce the number of lines connected to the data bus and simplify the configuration...-
The objective is to reduce the amount of deware.

[Summary of the Invention] The main point of the present invention is that a secondary device (for example, a peripheral device) with a small number of parallel transfer bits is connected only to the part of the data bus that accommodates the number of parallel transfer bits (or bytes), and A transfer control device (e.g., main memory control device) connected between the data bus (e.g., main memory device) and the data bus switches the specific portion of the data bus to a desired portion of the main device (e.g., a desired area of the main memory device). It's where I tried to connect it. The control information for the switching connection by the transfer control device is given to the transfer control device from the sub-device via an appropriate control line.

[Embodiments of the invention]

FIG. 3 shows an embodiment of the present invention in which a peripheral device accesses a main memory device via a 2-byte wide data bus. Arithmetic processing unit (hereinafter referred to as BPU) 1, selector board (hereinafter referred to as 5-PORT) 2
and multiplex support (hereinafter referred to as M-PORT)
3 is an example of a peripheral device. S-PORT 2 generally corresponds to what is called a selector channel or block multiplexer channel. These peripheral devices and main memory controller (hereinafter referred to as MSC) 4 are
C data bus byte 0 (hereinafter referred to as 5DBUS 0)
IO and MSC data bus byte 1 (hereinafter referred to as 5DBUS)
BPUI and 5-PORT2, which transfer 2 bytes of data at a time, are connected to both data buses; M-po-aT3 connecting a low-speed input/output device with only 1 byte of data
is connected only to 5DBUS111. M3C4 has MS data bus byte 0 (hereinafter referred to as MDBUSO) 20 and MS data bus byte 1 (hereinafter referred to as MDBUS).
21 (referred to as I), the byte 0 side of the main memory (
It is connected to the byte 1 side (hereinafter referred to as MSI) 5a and the byte 1 side (hereinafter referred to as MSI) 5b, respectively. BPUl, 5-PO
An MSC address bus (hereinafter referred to as 5ABUS) 1 is connected between each of RT2 and M-PORT3 and MeO2.
8 and M8C interface control line groups 30a, 30b,
30C is connected, which is the power fMSO5a and IVIS
Control information for referencing or updating the contents of 15b is transmitted. Details of the M8C interface control line group will be explained later.

Inside MeO2, byte 0 is used for data transfer control.
There is a data selection circuit 40 and a byte 1 data selection circuit 41, and the operation of these selection circuits is controlled by the data selection control circuit 6 via a byte 0#P data selection instruction control line 50 and a data selection control line 51, respectively. controlled by This data selection control circuit 6 controls the main memory access source 1 to
3 to M8C interface control lines 30a~
Receive control information via 30C and 5ABUS18,
In addition to performing the above control, the main storage devices 5a and 5b are also controlled. Note that the main storage devices 5a, 5 using MeO2
Since the control of b and each access source 1 to 3 is the same as the conventional one, detailed explanation will be omitted.

FIG. 2 shows the MSC interface control line group 302 to 30.
The details of one set in 1L are shown. 5REQ31 is a request line for access to the main memory, and 5ACP32 is a response line for replying to the request source that the access request has been accepted. If multiple access requests conflict with each other, they are processed according to predetermined priorities. The access source, informed by the 5ACP32 that the access request has been accepted, refers to the address of the main memory to which it wishes to update.
In addition, in the case of updating, it sends update data to 5DBUSO10 and 5DBUSI11, and also sends the following control information for various operations to be performed by the MSC4 to the MSC interface control line group 308 to 30. The signal is sent to the corresponding signal line. This procedure is basically the same as the conventional one.

R, /W FLAG32 indicates whether to refer to or update the main storage device 1-1 "0" indicates reference mode, PA1'" indicates update mode. PWTFLAG34 is a partial write instruction line, "0" Then write 2 bytes simultaneously, “1”
If so, it indicates a 1-byte partial write.

However, this signal is in update mode, i.e. R/WFL
Valid only when AG 32 is P1'''.

BGFLAG35 is a valid data byte position change instruction line, and if it is “0”, it is normal mode, that is, 5DBUS.
Indicates the connection between O and MDBUSO, 5DBUSI and MDBUSl, and if “1” indicates the change mode, that is, 5DBU
Instructs to connect SO and MDBUS1, and 5DBUS1 and MDBUSO. Note that 5END36 is a signal line used to report to each access source that the main storage device reference or update operation has been completed.

In this embodiment, in order to simplify the explanation, it is assumed that one set of these MSC interface control line groups 308 to 30C6- is provided between each access source 1 to 3 and MS, C4. It goes without saying that the number of signal lines can be reduced by making part of the bus structure common (wired-or).

Figure 3 shows the R/W of the MSC interface control lines.
FLAG33. PWTFLAG34 and BGFLAG3
5 and 5ABUS (3, 7), which is the least significant bit of the main memory address on 5ABUS1B. M
FIG. 4 schematically shows the flow of data between DBUSO,l. In addition, in FIG. 4, the representation that a bus drawn with a dotted line ends with an X mark means that the main memory data at that byte position is not updated.

BPUI and 5-PORT 2 connected to both 5DBUSO10 and 5DBUSI 11 are case A in Figure 4.
Main memory can be accessed by any of ~H. For example, case A is for a normal reference operation, and case C is for an update operation. BGFLAG3
It goes without saying that the byte position can be changed by setting 5.

Access to the main storage device by M-PORT3 connected only to 8DBUS111 is in Cases A and B.

Performed by F or G. First, refer to the main memory (
In the case of data transfer to a low-speed output device connected to M-PORT 3), M-POI-LT 3 detects that 5ACP 32 has become "1" and sends the main memory address to be read to 5ABUS18. At the same time, the control line R, /WFLAG33e is set to "0"" to indicate the reference mode. At the same time, ・IIGFLAG3
5 is set to 1'' when the data of MSO 5a is required (Case B), and is set to 0'' when the data of 1MSI 5b is required (Case A). In this case, the As shown, 5AI3US(3,7) is ignored as far as the control of the data selection circuit 40.41 is concerned. Upon receiving this information, the MSC4 reads data from the specified address of the main memory to the MDBUSO9l. At the same time, assuming that P/WFLAG33 is ``0'', BGFLAG35 is ``0'' f6?
1"ff) or (C), the data selection control circuit 6 is connected to the data selection circuit 40.41 via the data selection instruction control line 50i'51.
control. By the above operation, BGFLAG35 becomes u
IT”, the data of MSO5a is 5DBUSI 1
1, t, BG, F'LAG35
”), !=e is M815b data is 5DBUSI
11, and both are transferred to M-PORT3. MSC4 has read data of 5DBUS0.1
Confirm that it has been reached and set 5END36 to u 1 u
and end the operation.

Next, when updating the main memory from M-FOR, T3, since M-FOR, T3 is connected only to 5DI3U8111, it will always be in partial write mode from 5DBUSI, and in the case shown in Figure 4. F and G are used. Therefore, R/WFLAG33 and PWTFLAG
34 are both set to "1'", and when writing to MSO5a, 5ABUS(3,7) is naturally "0"".
BGF'LAG35 is "'1"' indicating the change mode, and when writing to MS15b, 5ABUS (3,
7) is naturally "'1'", and BGFLAG35 is "o" indicating the normal mode. In response to these control information, the MSo4 transmits data from the data selection control circuit 6 to the data selection circuit 40 via data selection instruction control lines 50 and 51.
．． 41 and operate the main storage device,
If BGFLAG35 is II OIt, update on the MSI side, if 1″, update on the MSo side, both with 5DBUS.
Based on the data on I11.

As an extension of this example, BPUI, 5-POI-LT
Similarly, when the data width of the data bus between the high-speed device such as 2 and MSo, 4 is 4 bytes or more, the data width of the data bus between the high-speed device such as M-P The data selection circuit can be controlled via control lines to transfer data between this and any part of the main memory to be referenced or updated.

FIG. 4 shows, as another example, BPUI and 5-POR
12 is a block diagram showing an example of a data selection mechanism when T2 and MSo4 are connected by a data bus with a width of 4) width, and M-PORT3 is connected to this with a width of 2/width. BPU and S-POE (, T is a 4-byte wide data bus lO~13 (SDBUS (1~3)
M-PORT is connected to 5DBU of these.
Assume that it is connected to S2 and S3. These data buses are connected to buses 20 to 23 (M
Connected to DBUSO~3). MDBUSO, 20 is set to 5DBUSOxo'y via data selection circuit 40.
Connected to DBUS212, MDBUSI 21 is connected to 5DBUSI 11 or 5DB via data selection circuit 41.
Connected to US313, MDBUS222 is connected to 8DBUS010 or 5DBUS21 via data selection circuit 42.
2, and the MDBUS323 is connected to the 5DBUSI 11 or 5DBUS3 via the data selection circuit 43.
13.

The control of the data transfer mode by the control signal in this embodiment is different from that in the first embodiment.
LAG34. BGFLAG35 and 5ABUS (3,7
) are substantially the same, except for some differences. In other words, in this embodiment, the PWT F L AG is a set of four lines, and writing is performed only for the byte corresponding to the line that is "1".
If any one of them is "0", a partial write is performed, and instead, SA, BUS (3, 7 companies become useless). 3 collectively controls whether to perform data transfer with MDBUSO and 1 or 2 and 3.

Note that byte position switching is not done in 2-byte units as described above, but by configuring a data selection circuit to transfer data between any 2-byte position where PWTFLAG is u1'' and 5DBUS2 and 3. Good too.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, by only adding a small number of control lines, it is possible to reduce the number of lines connected to the data bus for a sub-device that requires a small data bus width, and thus , it is possible to simplify the configuration of the sub-device and reduce the amount of hardware, and also to solve the problem of the number of pins (so-called bin neck) when implementing LSI.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a diagram showing details of the ink face control line group in Fig. 1, and Fig. 3 is a diagram showing the correspondence between control line signal combinations and operation contents. Figures 4 (1) to (8) are schematic diagrams of data flows corresponding to the operations shown in Figure 3, and Figure 5 is a block diagram showing the main parts of another embodiment of the present invention. be. ■... Arithmetic processing unit, 2... Selector board, 3...
...Multiplexer board, 4...Main memory control unit,
5a-5d... Main memory device, 6... Data selection control circuit, 40-43... Data selection circuit, 10-13.
...MSC data bus, 18...address bus, 20
~23...MS-7-Tabas, 308~30C...
Interface control line group. Agent Patent attorney Mamoru Nohagi (and 1 other person) First bacterium No. 30 h4T contents ゛θ s □ Reverse Scent Sys p./I OOM, 5 'y-''<, E///I/M, c person Su A-#kL w-qr Carp 4 (2) (1) k's A (RD) (2 ))y-7,8(RD-
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, Title of the invention Data bus system 3 for a group of devices with different required data bus widths, Relationship with the case of the person making the amendment Patent applicant address (residence) 4-6 Kanda Surugadai, Chiyoda-ku, Tokyo Name (Name) 510) Representative of Hitachi, Ltd.
3 1) Shigeru Katsutoshi 4, agent address (residence) 2-7-9-6, Toranomon, Minato-ku, Tokyo, subject of amendment (a) Column for brief explanation of drawings in the specification (b)
Drawing (Figure 4) 7. Contents of amendment (a) End line of page 14 of the specification “(1) -
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Claims (1)

[Claims] 1. A main device, a data bus with a width of a small number of bits, a group of sub-devices that transfer data between the main device via the data bus, and a group of sub-devices interposed between the MiJ data bus and the main device. An information processing device comprising a transfer control device and a control line group provided between the sub-device group and the MIJ transfer control device, the sub-device group including a sub-device having a smaller number of parallel transfer bits than the others. In the above, the sub-device with a small number of parallel transfer bits is connected only to a part of the data bus; and which part of the main device the data transfer is to be performed between, and the transfer control device controls the data bus and the main device in response to the instruction of the control line. A data bus system characterized by the provision of data selection means for switching connections between