JPS60138662A - Processing equipment control method - Google Patents

Abstract

PURPOSE:To change the performance of a processor according to a program stored in a memory by varying the transmission timing of an answer signal to the processor in accordance with a memory block to which an access request is given. CONSTITUTION:An answer signal RDY control circuit 1 sends a RDY signal corresponding to the access time of a memory to which an access is sent back to a CPU2 against a processor request PRQ signal given from the CPU2. In other words, the period during which the signal PRQ is produced and the signal RDY is sent back is changed dynamically in response to an access address. Therefore a memory block 4 can be formed with memory blocks 4a and 4b having different access times. For instance, a program requiring the high-speed processing and a program having no inconvenience with the low-speed processing are stored to the memory 4a of high cost and the memory 4b of low cost respectively. As a result, the performance of a processor can be changed according to the program stored in the memory.

Description

[Detailed Description of the Invention] +8) Technical Field of the Invention The present invention relates to a system in which a processing device accesses memory in response to a response signal to an access request signal, and in particular, it is possible to adjust the performance (processing capacity) of the processing device. This invention relates to a control method for a processing device.

(bl) Prior Art and Problems Conventionally, the access time for accessing a memory or the like based on a request from a CPU has been fixed, and high speed has generally been desired.

However, not all users necessarily require high-speed processing, and even if low-cost memory with a long access time is sufficient for the purpose, it may not be possible to easily connect it to a CPU and use it. There were times when it was difficult to do. For this reason, there has been a problem in that it is difficult to provide a computer system with high cost performance that meets the user's application.

FIG. 1 is a diagram illustrating a conventional memory access operation.

1 shows a CLK signal waveform, that is, a clock signal waveform for synchronously controlling the CPU and the like, and shows a series of signal waveforms in which the memory and the like are accessed in cycles T1 to T4.

Figure 1 ■ shows the PRQ signal waveform, that is, the processor request signal (PRQ) that requests access from the CPU to memory, etc.
(signal) waveform, and shows a signal waveform at which an access operation of a memory or the like is started based on the PRQ signal.

Figure 1 ■ shows the data waveform, for example, DO to D15.
This shows the waveform when data consisting of is read from the memory and supplied to the CPU. The data is valid CP tJ
The illustrated memory access time and Ecc (error check) time are required to read the data. The memory access time is the time during which data is read from the memory, and the Ecc time is the time required to check the read data for errors, and to perform automatic correction if there is an error.

Figure 1 ■ is the RDY (re a dy) signal waveform,
In other words, in response to an access request from the CPU, C from memory etc.
A signal waveform for notifying the PU of access preparation completion is shown. Based on the RDY signal, the CPU reads the data at the falling edge of the next machine cycle T4 ((2) in FIG. 1).

As described above, conventional CPUs generally access memory and the like using fixed, predetermined machine cycles, in the example described above, four machine cycles, and are intended to operate as quickly as possible. For this reason, it has been difficult to use, for example, an inexpensive memory with a slow access time in accordance with the user's application with a simple configuration. In addition, if the speed of the CPU machine cycle is reduced in order to connect to memory, etc. that has a slow access time, the high-speed processing ability of the CPU will be reduced, making it difficult to improve the cost performance of the computer system. There was a problem in that it became impossible to maintain a high level of performance.

(C) Purpose of the Invention The purpose of the present invention is to solve the above-mentioned conventional problems.
An object of the present invention is to provide a control method for a processing device that can change the performance of the processing device according to a program stored in a memory.

(dl Structure of the Invention In order to achieve the above object, in the present invention, in a system where the memory for storing a program is composed of a plurality of blocks, a memory block accessed by a processing device is identified by an access address, and based on the identification result, , the memory access cycle period can be set according to the access time of the memory block to which the access request has been made.

Hereinafter, the present invention will be explained in detail using Examples.

(el Embodiment of the Invention FIG. 2 is an embodiment of the present invention, FIG. 3 is an explanatory diagram explaining the operation of one embodiment of the present invention shown in FIG. 2, and FIG. 4 is RI shown in FIG. 2) A specific example of a control circuit.

FIG. 5 is an explanatory diagram illustrating the operation of a specific circuit example of the RDY control circuit shown in FIG. 4.

In the figure, 1 is an IMADY control circuit, 2 is a CPU, 3 is a memory control circuit, 4 is a memory block, 5 is an EcC control circuit,
6 is PRQ signal input terminal, 7 is RDY signal output terminal, 8 is
．． [3 is a flip-flop circuit at J-, 9 is a counter,
10 is a comparator.

Reference numeral 11 indicates a setting circuit, and reference numeral 12.14 indicates an AND circuit.

In FIG. 2, the RDY control circuit 1 is a circuit for returning to the CPU 2 an RDY signal corresponding to the access time of the memory to be accessed in response to the PRQ signal from the CPU 2.

In this embodiment, the time from when the PRQ signal is issued by the CPU 2 to when the RDY signal is returned can be dynamically changed depending on the access address. This makes it possible to configure the memory block 4 into memory blocks 4a and 4b- each having a different access time (that is, the time from when an access request is issued until memory access is actually possible).

As a result, for example, a program that requires high-speed processing (high performance) can be stored in the high-speed/high-cost memory 4a, and a program that can handle low-speed processing (low performance) without any problems can be stored in the low-speed/low-cost memory 4b. It is possible.

The Tongfu program is divided into the following tiers.

■Kernel section■Various drivers (disk drivers, NESOT work dryers, etc.) ■Various hunters (disk handlers, NESOT work handlers, etc.) ■Various monitoring programs (file system managers, network managers, etc.) ■Applications Programs Each of these programs has access frequency and CPU
Performance requirements differ. Therefore, by setting the memory blocks in which each hierarchical program is stored in accordance with the CPLI performance required for the program, a system with excellent cost performance can be constructed.

For example, among the above programs, each of the programs ① to ② requires high-speed processing by the CPU,
The data is stored in the high-speed/high-cost memory block 4a. On the other hand, each of the above-mentioned programs (1) to (2) does not necessarily require high-speed processing by the CPU. Therefore, each of these programs is
The data may be stored in the low-speed/low-cost memory block 4b. Also, in terms of memory capacity, the programs (1) and (3) above require a large amount of memory space, and from this point of view, cost performance can be improved.

The RDY control circuit 1 selects a memory block 4a, which has an access request, according to the memory address output from the CPU 2.
4b. Based on the identification results,
The return timing of the RDY signal is determined in accordance with the access time of the memory block to which the access request is made.

The memory control circuit 3 to which the PRQ signal from the CPU 2 is input supplies, for example, a read signal or an address signal for reading to the memory processor 4. Then, after a predetermined access time has elapsed, predetermined data is read from the memory block 4 and input to the ECC control circuit 5.

The ECC control circuit 5 uses error check bits included in the read data to detect whether there is an error in the data, and if there is an error, performs processing such as automatic correction.

After predetermined processing is performed by the ECC control circuit 5,
The CPU 2 completes a series of accesses by reading the data.

Further, the CPU 2 can also write predetermined data into the memory block 4 via the ECC control circuit 5.

Figure 3 ■ shows the CLK signal waveform, and the machine cycle TI
, T2. T3. Waveforms consisting of T4 and Tw are not shown. T
w indicates a state in which the CPU 2 is in a standby machine cycle.

3 shows a PRQ signal waveform requesting access from the CPU 2 to a memory or the like.

Figure 3 ■ shows data DO or D read out from memory.
15, and the data output signal waveform from the ECC control circuit 5 is shown. The time for the CPU 2 to read data DO to D15 from the data output signal waveform is the memory access time for reading data from the memory block 4 and the Ecc time required for checking the read data for errors. It will be a time of peace with. E
By spending the cc time, the reliability of the read data is increased.

3 is the RDY signal waveform, and at the falling edge of the next machine cycle (falling edge of machine cycle T4) after which the RDY signal waveform was sent, the CPU 2 receives the data D.
The signal waveform for reading 0 to D15 (Fig. 3 ■) is shown. In the case shown in FIG. 3, the timing of issuing the RDY signal is delayed by one cycle compared to the case shown in FIG. The RDY control circuit 1 measures the timing and notifies the CPU.

FIG. 4 is a diagram showing a specific circuit example of the RDY control circuit 1 shown in FIG. The setting circuit 11 in the figure is, for example, R
It is composed of OM and is supplied with memory addresses output by the CPU 2. Then, the memory block to which the access request is made is determined from the given address, and the number of standby cycles of the CPU 2 is set in accordance with the access time of that memory block. The operation of the circuit shown in FIG. 4 will be explained below using FIG.

When the PRQ signal (■ in Figure 5) issued by the CPU 2 is input to the PRQ input signal terminal 6, the flip-flop circuit 8 is sent to J- at the falling edge of the T1 cycle of the CLK signal, and an H level FO multiplied signal is output. (Figure 5 ■arrow).

As a result, the counter 9 outputs the CLK signal (■ in Figure 5)]
The number B1 is counted at each falling edge of the 2 cycles and the 2 cycles. The counted value is input to the comparator 10.

On the other hand, the setting circuit 11 is given a memory access address requested by the CPU 2. Assume that this address is, for example, an address on the low-speed memory 4b. The setting circuit 11 is
The memory to which this access request is made is determined, and the number of standby cycles of the CPU 2 (in this case, "2") is output in accordance with the access time of this memory.

The number of standby cycles set by the setting circuit 11 is input to the comparator 10. The comparator 10 compares the given number of standby cycles with the count input from the counter 9, and if they are equal, the comparator 10 outputs an H level signal to the AND circuit 12. The AND circuit 12 inputs H from the flip-flop circuit 8 to J-.
The H level signal which is the result of AND logic with the H level signal from the comparator 10 is J-
is input to the flip-flop circuit 13. When the CLK signal is input to the flip-flop circuit 13 to J-, 1
A 1 level F1 signal is output (arrow in Figure 5). The F
1 signal is sent in the last cycle of the standby cycle Tw, and the AND logic of the F1 signal and the FO multiplied signal is taken by the AND circuit 14, and the RDY signal at H level (the It is output as (■) in Figure 5.

Then, the flip-flop circuit 8 is reset to J- by the falling CLK signal of the last cycle Tw, and the FO multiplier signal (Fig. 5)) and the RDY signal (Fig. 5 ■) are set to L level, and the counter 9 Reset to initial state. Furthermore, the flip-flop circuit 13 is reset to J- by the falling CLK signal (■ in FIG. 5) in the next cycle T4, and the F1 signal (■ in FIG. 5) becomes L level.

(fl) Effects of the Invention According to the present invention, the timing of sending a response signal to a processing device can be varied according to the memory block to which an access request has been made, without deteriorating the processing performance of the processing device. In addition, it is possible to construct a system with high control performance using low-cost memory and the like.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram explaining conventional memory access;
The figure shows one embodiment of the present invention, and FIG. 3 shows the second embodiment of the present invention.
FIG. 3 is an explanatory diagram illustrating the operation of the embodiment. FIG. 4 shows a specific circuit example of the RDY control circuit shown in FIG. 2, and FIG. 5 shows an explanatory diagram illustrating the operation of the specific circuit example of the RDY control circuit shown in FIG. In the figure, 1 is an RDY control circuit, 2 is a CPU, 3 is a memory control circuit, 4 is a memory block, 5 is an EcC control circuit, and 6
7 is a PRQ signal input terminal, 7 is an RDY signal output terminal, and 8.
13 is a flip-flop circuit at J-, 9 is a counter, 1
0 is a comparator. 11 represents a setting circuit, and 12.14 represents an AND circuit.

Claims (1)

[Claims] a processing unit; a memory comprising a plurality of memory blocks;
A system comprising: a memory control circuit that accesses the memory based on an access request signal output by a processing device; and the processing device accesses the memory in response to a response signal returned in response to the access request signal; a setting means for setting a return timing of a response signal to the access request signal according to address information for memory access output by the processing device; and a setting means for returning the response signal to the processing device at a timing specified by the setting means. 1. A control method for a processing device, comprising: a control circuit for changing a return timing of a response signal to an access request signal according to an access time of a memory block to which the processing device requests access.