JPS60136995A - Nonvolatile ram - Google Patents

Abstract

PURPOSE:To attain a RAM suitable for high circuit integration and the write by a single 5V power supply by connecting the 1st and the 2nd gates in series between the source and drain of a ROM via an insulation thin film and injecting electrons to the 2nd gate from a channel near the connecting point. CONSTITUTION:When the information of an SRAM100 is at L level, the level of a node Q is at L, no current flows from a drain 15 in an E<2>PROM101 to a terminal ERS of the source 14 and no electronic write to a floating gate FG is conducted. When the information of the SRAM100 is at H, the level of the node Q is at H, a current flows from the drain 15 to the source 14, and electrons are written from the vicinity of the boundary between channels l1 and l2 to the floating gate FG via a thin insulation film tox2. The floating gate FG is charged electrostatically positively by a signal at the terminal ERS, shifted positively by a share of voltage VDD by a coupling capacitance of a control gate CG, the electric field toward (y) is stronger and the write voltage becomes lower.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonvolatile RAM (hereinafter referred to as NVRAM) that is suitable for high integration and that can be written to with a 5vHt power supply.

Conventional NVRAMs have a large number of elements, making it difficult to increase the degree of integration. The present invention overcomes this drawback,
The object of the present invention is to obtain an integrated circuit (hereinafter referred to as process C) with high integration and large memory capacity. Examples of the NVRAM according to the present invention are shown in FIGS. 1(a), 2, 3, 4, and 5.

The first embodiment of the NVJ'tAM of the present invention will be described using FIG. 1 (8).

This NVRAM has four modes of operation. That is, %(i) SRAM10Q (static R
AM) reading).

(4) Write sRAuloo.

■ ROM10 that can be electrically rewritten from SRAM100
1 (hereinafter referred to as Fi2PR0M) (hereinafter referred to as Store 匍1 work), ■ is FROMl 01 to 5FIA'M1
There are four operation modes: data transfer to 00 (hereinafter referred to as recall operation).

1) Since the SRAM 100 has two operation modes: (1) read and (2) write, these two operations will be explained first. At this time, the terminals VRO and φ in FIG.
The respective voltages of the B engineering T, the world line WL, the terminals n() and SG are applied as shown in No. 11xl(b). Here, H is the VυD level and L is the ground level. ■ Noriichido's action i, CMo5's Fl Fl A M 10
A difference occurs between the voltage levels of the bit lines BL and BL depending on the information of the 0 cell. This difference is measured by a sense amplifier (not shown).

) and output it, it is possible to read out the SRAM 100. On the other hand, in the write operation (2), the voltage is applied to each of the pits aBL and BLi, or vice versa, depending on the write information. At this time, the word line WL is H
Then transistors 5 and 6 are turned on (, so they are forced to beep)! The information on BL and 1 is written into the cells of the SRAM 100.

2) Next, store operation (write) of K”PP0M101
For example, the timing diagram in Figure 1(c), the cross-sectional structural diagram of K"PRO'M 101 in Figure 1(ρ), and the K"FRO'
This will be explained using FIG. 1(f) showing the characteristics of Mlol.

The terminal VRO in FIG. 1(8) is biased to VDD, and the terminal φ and the word line are biased to ground. Also terminal ER
8. Signals are applied to the terminals CG and SG, respectively, as shown in FIG. 1(c). Therefore, terminal φ seedling beam, terminal VR
C is applied to H.

At this time, when the signal at the terminal ER8 is raised to a high voltage as shown in FIG. 1(c), a Fowlθv−Novdheim current flows between the terminal ER8 and the floating gate 700 in FIG. . Therefore, the electrons in the floating gate FG are connected to the terminal KR.
8, the floating gate FGll-i becomes positively charged due to the lack of electrons, and becomes the depletion threshold in the channel lr'. That is, as shown in the characteristic of FIG. 1(f), the current characteristic of the K"FROM 101 shifts from the initial state a to the erased state C. Next, the signal at the terminal FiR8 is lowered, that is, set to L, and the control gate terminal CG When the signal of select gate terminal SG is raised, that is, HK
Then, depending on the information in SRAM1'O0, electrons may not be written to the floating gate PG or may not be written to the proper amount. That is, when the information in the SRAM 100 is H, the node Q is H, so Tff12FROM 101
A current flows from the drain 15 to the source 14. At this time, a sudden change in the thermal temperature occurs near the boundary between channels e and electrons are accelerated here. Also, since the floating gate FG and the control gate terminal CG are strongly coupled through the thin insulating film tOX4, the control gate terminal C
An electric field is applied in the Y direction near the insulating film tox2 by the G signal, and the accelerated electrons are written into the floating gate terminal FGK with a certain probability. Since the FG is surrounded by an insulating film, the electrons once written will not be lost. Therefore, the floating gate) PG is negatively charged, and the channel! , the threshold value of , is changed to an enhancement threshold value, and the W''FROM 101 has the characteristic of the write shape 9b in the characteristic diagram of FIG. 1(f).

On the other hand, when the information in the SRAM 100 is L, the node Q is L
Therefore, no current flows from the terminal drain 15 in FJ'FROM 1.01 toward the terminal EBS of the source 14. Therefore, there is no sudden change in the potential, and no electrons are written into the floating gate (PG), so the characteristics of pRoM101 are also the same as the erased state C in Figure 1(f).
It remains as it is. In this way, by utilizing the difference in characteristics between the erased state PC and the written state shown in FIG. 1 (f>K), the SRAM
100 information 'eli! "It is possible to write into the FROM 101. Next, another example of the store operation will be explained.

This store operation is performed by deleting the signal at the terminal ER8 shown in FIG. 1(C) and applying the signal to the control route CG and select gate terminal SG as shown in FIG. 1(a).

That is, initially the characteristics of g2pRoM'i o 1 are shown in Fig. 1 (f
This is possible by moving the characteristics of the 2PFtOM 101 to the erased state 3 by performing ion implantation in the channel 711 under the floating gate F'G. To explain the operation, in the initial state after ion implantation, m2PROM10
The characteristic of 0 has a depression threshold as in the erased state C in FIG. 1(f).

The information of SRAM100 is L, and the node Q is L,
Drain 15 to source 1 in E"FROM 10'1
No current flows through the terminal FiR8K of No. 4, and therefore no electrons are written into the floating gate FG. Therefore, the characteristics of mlPROM j 01 maintain the erased state cf shown in FIG. 1(f). If the information in SRAM 100 is H, node Q is H and F! A current flows from the drain 15 in the 2F ROM2O3 to the terminal KR8 of the source 14, and electrons flow from the vicinity of the boundary between the channel β1 and the channel E2 to the floating gate FG via the thin insulating film tox2. Get the right size.

Therefore, the characteristics of the criminal 2PROM i 01 are as shown in the writing pattern ib shown in FIG. 1(f). Therefore, due to the characteristics of write state for each erase state of 11'X1(f), m"FROM
Information of the SRAM 100 can be written in 1 o 1.

Comparing the two store operations, the input voltage is lower when the terminal TLRBVc signal is present.

This is because the signal at terminal KR8 charges the 70-ting gate PG positively, and furthermore, the control gate cG
Since the coupling capacitor causes a positive shift by the voltage VDD, the electric field in the y direction becomes stronger, and the write voltage is unusually low.

3) Next, the circuit diagram of the recall operation is shown in Figure 1 (a), the timing diagram of the recall operation is shown in Figure 1 (g), and the K2FR.
Figure 1 (θ) showing the structure of OM 101 and E”PRO
This will be explained using FIG. 1(f) showing the characteristics of M101.

The state of S]'tAM100 before entering the recall is the state T
n' I, and the state of the SRAM 100 after recall is called state Tn. Let us consider a case in which a recall signal is input using the same timing as Q in FIG. 1 when the information in the SRAM 100 is H in state Tn-8. FIG. 1 (When the terminal VR○ falls and the 9 terminal φBIT and the word iwb rise as shown in W). , is half level (approx. around VDD)
, the nodes are mutual. ■ Become.

Thereafter, as shown in Figure 1), when the terminal φBXT and the word line WL fall, the node Q becomes the level of VTP and the node Q becomes OV.

When the information in the SRAM 100 is L in one-sided pTn-, the terminal VRa falls as shown in FIG. 1(g) VC,
When the terminal tjyBxc and the word line WL rise, the node Q becomes half level (approximately VDD) and the K node i becomes 0V.After that, as shown in Fig. 1(g), the terminal φB and the word line When line WL falls, node Q.

is VTP C1v Hell K, and node b is oVVc.In the end, as shown in the first IMI (g), before the select gate terminal SG rises, the 8RAM10 is in the state Tn-1.
Regardless of the information of 0, the node Q1 becomes OVK at the vTP level. In this state, select gate terminal 8G
When the voltage is raised as shown in Figure 1, the potential of the node Q is determined depending on the presence or absence of electrons in the floating gate 11 of the transistor 7 in Figure 1(a). The potential of the floating gate F() is proportional to the potential of the control gate terminal CG, which has a large amount of capacitive coupling, and the amount of written electrons.

Therefore, when electrons are being written into the floating gate 11, that is, when there are electrons in the floating gate 11 (this is called the store 1 state), holes are induced in the channel l under the floating gate PG, and E
2FROM1'01 (7) The current characteristics are as shown in the write state shown in FIG. 1(f), and no current flows when Vco=OV. However, VOG indicates the voltage applied to the control gate. Therefore, node Q remains at VTP level,
Node d is at Ov. At this time, as shown in FIG. 1(g), when the voltage at terminal via is gradually raised, node Q becomes H and the other nodes become L.

On the other hand, if the floating gate 11 is not written with electrons, that is, if there are no electrons in the floating gate 11 (when this state is 0), the channel of the floating gate FGF! , Haga PROM1'01
Since the characteristic of is the erased state C in FIG. 1(f), vce
=ov, a state is reached in which current flows between the drain 15 and the source 130. Therefore, when the signal to the select gate terminal 8G rises, the wealth and charge of the node Q are discharged, and the node Q becomes O.
It becomes V, and the node stone also remains OV. The stray capacitance existing between node Q and node Q and VC is inevitably larger at node Q depending on the number of transistors connected. At this time, if the voltage at terminal VRO is slowly raised, node Q.

Both nodes are 0V, but due to the difference in stray capacitance,
The establishment of node Q is delayed, and the state of node Q is determined to be H in nodes o, ij, and L. In this way, it is possible to write information to the SRAM 100 before the store, write it once to the FROM 101 by the store operation, and then recall it from the Ilf12FROM 101 to the 8RAM 100 by the recall operation.

From the above, the circuit of FIG. 1(a), which is the first embodiment, can perform the read/write operations inherent to the 19RAM 100.

■ SRAM100 data iFi by store operation
Can write to 2FROM 101 and K”FR
The data in OM 101 is non-volatile, so the information will not disappear even if the power is turned off.

■ T by recall action! ``Data from FROM 101'' iSRAM i OOr/c can be recalled.

■ E"FROM 101 Even if it stores K data, the SRA 14100 can be used as a normal SRAM regardless of its operation.

Therefore, it completely satisfies the original functions of nonvolatile RAM. Katsu C! S RAM 100 consisting of M OS
Since it is constructed by adding only one transistor to the circuit, the circuit is a cylinder and the cell area is small.
This is the optimal configuration for obtaining a highly integrated process C.

Fig. 2 shows the first embodiment shown in Fig. 11M1(a) with a capacitance 12 added to stabilize the recall operation, c, 4! "When recalling the state of store 0 of PftOMl 01, in FIG. 1(a), using the difference in stray capacitance, the SRAM1 is
00 was determined, but by adding Kg-[12 on the node Q side, there is a further difference in the rises between the )-do Q and the nodes, making it possible to operate stably.

When recalling the state of store 1, the operation is exactly the same as in the first embodiment, regardless of the capacity 12.

As described above, according to the second embodiment shown in FIG. 2, a nonvolatile RAM with even more stable recall operation can be obtained.

FIG. 3 is a simplified version of the first embodiment shown in FIG. 1(a). In the circuit diagram of Figure 1(a).

As seen in the structural diagram of FIG. 1 (θ), spring insulation Jpi! erases the electrons in the floating gate FG!
Fowlev-No from terminal ER8 via tox1
It was unplugged as rdhpim current.

In FIG. 3 showing the third embodiment, the electrons in the floating gate FG are erased from the select gate terminal 8G via a thin insulator III tOX5'fc. According to this sixth embodiment, the terminal E in FIG. 1(p)
There is no need to apply a high voltage to R8, and it can be fixed at 0V. Therefore, the distance between the N+ source 14 and the P+ channel stopper (not shown) may be close, which helps increase the degree of integration of the memory cell section.

FIG. 4 shows a further cylindrical portion of FIG. 3 showing the third embodiment, and the transistor 7 in the F"PR,OM 102.
In this case, the control gate terminal 0'G, which was strongly capacitively coupled to the floating gate PG, was omitted.

FIG. 4 shows the fourth embodiment, in which the control gate terminal CG is omitted.
This is an example of a circuit that functions similarly to the third embodiment.

FIGS. 5(a) and 5(b) show a fifth embodiment in which a constant voltage is not applied to the memory cell 102 shown in FIG. 1(a), and in particular, the memory cell 102 shown in FIG. Ej”P E
This is an example carried out to improve data retention characteristics in a 0 Mlol cell. Note that the memory cell array 10
3 consists of a large number of memory cells 102C:.

In FIG. 5(a), a constant voltage from the Vpp side is received by the gate of the transistor 13 of the FOB. The transistor 13 operates as a constant current operated in the saturation region, and all fluctuations in the power supply voltage VDD are absorbed as the voltage between the source and the source 747 of this transistor 13, so the voltage applied to the memory array 103 becomes constant. E'FROM10
When the cell circle is 1, the terminal SGF is
:r, L level, and no current flows through the transistor 7 of FIG. 1(a), but a slight off-leak current flows.

When the voltage applied to the E2FROM Mi01 cell increases, this off-state current increases, and eventually electrons are written to the floating gate (PG), making it impossible to retain the original data. In order to prevent such negative effects, constant voltage and constant current circuits are used to
191 (FL) is a circuit designed to stabilize memory retention characteristics by applying only a constant voltage to the memory cell 102.

Figure 5(b) shows a constant voltage/constant current circuit that receives a constant voltage from the ground side through an NchMO8) transistor, and similarly only a constant voltage is applied to the memory cell 102 to stabilize the memory retention characteristics. It is a circuit.

Figure 6 shows a memory cell 10 connected in series with constant voltage circuits.
This circuit aims to stabilize the memory retention characteristics by applying a constant voltage to 2.

In this way, according to the present invention, C! 5Ft consisting of M5 S
Since a non-volatile RAM'i can be realized by adding only one transistor to A'M100, the area of the memory cell can be reduced. Furthermore, as in the embodiment of Kg2, a floating gate is connected from the select gate terminal SG.
By removing electrons from FG, the area of the memory cell can be further reduced.

Therefore, the present invention is the most suitable circuit for large-capacity, highly integrated circuits, and is suitable not only for memory ICs but also for custom ICs.
It is also used as a cell for incorporating C, and its application fields are extremely wide.

[Brief explanation of drawings]

FIG. 1(a) is a circuit diagram of a first embodiment of the nonvolatile RAM of the present invention. Figure 1(b) is a diagram showing the voltage values applied to each terminal (C) during normal operation of the SRAM. Figure 1(a) is an example of a store operation from SRAM to E''P and ROM. Timing diagram. Figure 1 (a) is a timing diagram of another example of the store operation from EIRAM to 2P and R0'M. The 11th button (θ) is the recall from E"FROM to 8 RAM M. Figure 1(f) is a timing diagram of the operation.
Fig. 2 is a circuit diagram of the second embodiment of the non-volatile FTAM of the present invention; Fig. 3 is a diagram of the third embodiment of the non-volatile RAM of the present invention. Example circuit diagram Figure 4 is a circuit diagram of a fourth embodiment of the non-volatile RAM of the present invention. Figures 5 and 5 (b) are the fifth embodiment of the present invention, respectively. A circuit diagram for optimal operation is shown in FIG. 6, which is a sixth embodiment of the present invention.
FIG. 7 is a circuit diagram for optimally operating M'ii'7. 1...P channel M01'! )Ran resistor 2...P
Channel MOB) Transistor 3...N channel M
O8) Ransistor 4...1J channel l#O8) Ransistor 5...N channel b'8) Ransistor...
・N-channel M08 transistor 7...N-channel M
O8) Transistor 8...P channel MO8) Transistor 9...P channel MOB) Transistor 10...
・N channel MOE! ), y resistor 11...floating gate 12...capacitor 13...P well substrate 14...N+ diffusion layer 15...N+ diffusion layer 16...N diffusion layer 17...first layer Polysilicon 18...Second layer polysilicon 100...SRAM 101...E''FROM 102...Memory cell 103...Memory array and above Applicant: Seiko Electronic Industries Co., Ltd. Agent Patent attorney Tsutomu Mogami Figure 1 C) ca ca-[]- 36-"]-36-[]- e Figure 2 Figure 4 Figure 5 (a) Figure 5 (b) Figure 56

Claims (1)

[Claims] A non-volatile RAM composed of a CMOS static RAM composed of a CMOS inverter and a ROM that can be written at 5V or less. (2) A first gate and a second gate are connected in series between the source and drain of the ROM via a thin insulating film, and electrons are injected into the second gate from a channel near the connection point. A nonvolatile RAM according to claim 1, characterized in that: (3) After precharging the output of the ('!MOS inverter), the channel under the first gate is made conductive to transmit the information of the ROM to the RAM. Nonvolatile RAM0 (4) A nonvolatile RAM0 according to claim 1, characterized in that a capacitor is connected to a node connecting the inverter output and the ROM'j7.