JPS60136320A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60136320A JPS60136320A JP24395183A JP24395183A JPS60136320A JP S60136320 A JPS60136320 A JP S60136320A JP 24395183 A JP24395183 A JP 24395183A JP 24395183 A JP24395183 A JP 24395183A JP S60136320 A JPS60136320 A JP S60136320A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- wiring
- sic
- conductor
- heat dissipation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000004020 conductor Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 8
- 229910010271 silicon carbide Inorganic materials 0.000 description 8
- 230000017525 heat dissipation Effects 0.000 description 6
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000004438 eyesight Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は絶縁基板に複数のＳｌチップが実装された半導
体装置、特に発熱量の多いＳｉチップの放熱に好適な半
導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device in which a plurality of Sl chips are mounted on an insulating substrate, and particularly to a semiconductor device suitable for dissipating heat from Si chips that generate a large amount of heat.
従来のこの種の半導体装置においては、例えば特開昭５
７−２５９１号に開示されているようにアルミナセラミ
ック基板（ＡＱ、Ｏ３板）にＷなどの配線を施している
。このＡＱ□０３基板の熱伝導率は小さいため、発熱量
の多い半導体素子を接続すると放熱が不十分となるとい
う欠点があった。In conventional semiconductor devices of this type, for example,
As disclosed in No. 7-2591, wiring such as W is provided on an alumina ceramic substrate (AQ, O3 board). Since the thermal conductivity of this AQ□03 substrate is low, there is a drawback that heat dissipation becomes insufficient when a semiconductor element that generates a large amount of heat is connected.
本発明の目的は放熱性能の高い半導体装置を提供するこ
とにある。An object of the present invention is to provide a semiconductor device with high heat dissipation performance.
炭化ケイ素（ＳｉＣと略す）は熱伝導率（０，６５ｃａ
ｌ／ ｃｍ−ｓｅｃ・℃）が高い絶縁材料であるという
点から放熱性能の高い多層配線基板材料に適していると
考えられてきた。しかし、ＳｉＣ上に従来の方法によっ
てＷメタライズなどの配線導体を作成しようとすると、
配線導体がはがれてしまうため、ＳｉＣを用いた半導体
装置は作られていない。Silicon carbide (abbreviated as SiC) has a thermal conductivity (0.65ca
It has been thought that it is suitable as a multilayer wiring board material with high heat dissipation performance because it is an insulating material with a high heat dissipation performance. However, when trying to create wiring conductors such as W metallization on SiC using conventional methods,
Semiconductor devices using SiC are not manufactured because the wiring conductors peel off.
そこで本発明者らは、鋭意検討した結果ＳｉＣへの配線
導体作成法として配線導体をＳｉＣへ拡散接合すること
を試みた。As a result of intensive study, the present inventors attempted diffusion bonding of a wiring conductor to SiC as a method for creating a wiring conductor to SiC.
以下、本発明の半導体装置の実施例を第１図。 An embodiment of the semiconductor device of the present invention is shown in FIG. 1 below.
第２図により説明する。第１図は断面図、第２図は第１
図のキャップを取り除いたものの平面図である。第１図
において貫通孔内にＡｌ１を入れられたＳｉＣ基板２は
Ａ Ｑ配線３と拡散接合され多層配線基板を形成してい
る。この多層配線基板の下面にはリード線４が付けられ
、上面にははんだ５を介してＳｉチップ６が接合されて
いる。多層配線基板には低融点ガラス７によってキャッ
プ８が取伺けられている。第１図において、配線導体は
ＡＱ以外にも、ＳｉＣ基板２と拡散接合が可能で、電気
抵抗の小さい金属であれば良い。又、貫通孔内に入れる
材料はＡＱ以外にも、貫通孔に充”Ｃん可能で電気抵抗
の小さい金属であればよい。This will be explained with reference to FIG. Figure 1 is a cross-sectional view, Figure 2 is the first
FIG. 3 is a plan view of the device with the cap shown in the figure removed. In FIG. 1, a SiC substrate 2 in which Al1 is filled in a through hole is diffusion bonded to an AQ wiring 3 to form a multilayer wiring board. Lead wires 4 are attached to the bottom surface of this multilayer wiring board, and a Si chip 6 is bonded to the top surface via solder 5. A cap 8 is covered with a low melting point glass 7 on the multilayer wiring board. In FIG. 1, the wiring conductor may be any metal other than AQ, which can be diffusion bonded to the SiC substrate 2 and has low electrical resistance. In addition to AQ, the material to be inserted into the through hole may be any metal that can fill the through hole and has low electrical resistance.
なお、配線導体をＳ ｉ Ｃ２に接合する場合、配線導
体は基板全面に渡り導体パターン加工を施したものを用
いる場合と部分パターン加工を施したものを用いる場合
がある。又、配線導体をエツチングにより形成し′Ｃも
よい。拡散接ａを完ｒした多層基板には配線導体の厚さ
にほぼ等しい微小隙間ができるため、強制空冷時にＳｉ
Ｃの放熱面積を増加させる効果がある。Note that when joining a wiring conductor to the S i C2, a wiring conductor that has been subjected to a conductor pattern processing over the entire surface of the substrate may be used, or a wiring conductor that has been partially patterned. Alternatively, the wiring conductor may be formed by etching. A multilayer board that has undergone diffusion bonding has a small gap approximately equal to the thickness of the wiring conductor, so Si
This has the effect of increasing the heat dissipation area of C.
本発明によれば、Ｓｉチップを熱伝導率の太きい材料に
拡散接合ができるので、放熱性能の高い半導体装置を得
ることができる。According to the present invention, since the Si chip can be diffusion bonded to a material with high thermal conductivity, a semiconductor device with high heat dissipation performance can be obtained.
第１図は本発明の半導体装置一実施例の断面図。
第２図は第１図においてキャップを いたも□のの平面
図である。
１・・・ＡＱ、２・・・５ｉＣ１３・・・ＡＱ配線、４
・・・リード線、５・・・はんだ、６・・・Ｓｉチップ
、７・・・低融点；ｉ′１ 目
才ｚｌ￥１FIG. 1 is a cross-sectional view of one embodiment of the semiconductor device of the present invention. FIG. 2 is a plan view of the bottom of FIG. 1 with the cap removed. 1...AQ, 2...5iC13...AQ wiring, 4
...Lead wire, 5...Solder, 6...Si chip, 7...Low melting point; i'1 eyesight ￥1
Claims (1)
半導体装置において、前記絶縁基板を熱伝導性材により
構成すると共に、この熱伝導体材と金属配線材を相互に
重ね合わせて拡散接合し、前記金属配線材を前記導体と
電気的に接合したことを特徴とする半導体装置。In a semiconductor device in which a Si chip is mounted on an insulating substrate having a conductor inside, the insulating substrate is made of a thermally conductive material, and the thermally conductive material and the metal wiring material are overlapped and diffusion bonded to each other, A semiconductor device characterized in that the metal wiring material is electrically connected to the conductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24395183A JPS60136320A (en) | 1983-12-26 | 1983-12-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24395183A JPS60136320A (en) | 1983-12-26 | 1983-12-26 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60136320A true JPS60136320A (en) | 1985-07-19 |
| JPH0444419B2 JPH0444419B2 (en) | 1992-07-21 |
Family
ID=17111459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24395183A Granted JPS60136320A (en) | 1983-12-26 | 1983-12-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60136320A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01302832A (en) * | 1988-05-31 | 1989-12-06 | Canon Inc | Electrical circuit device |
-
1983
- 1983-12-26 JP JP24395183A patent/JPS60136320A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01302832A (en) * | 1988-05-31 | 1989-12-06 | Canon Inc | Electrical circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0444419B2 (en) | 1992-07-21 |
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