JPS60132344A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60132344A JPS60132344A JP24031083A JP24031083A JPS60132344A JP S60132344 A JPS60132344 A JP S60132344A JP 24031083 A JP24031083 A JP 24031083A JP 24031083 A JP24031083 A JP 24031083A JP S60132344 A JPS60132344 A JP S60132344A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- oxide film
- semiconductor device
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000010410 layer Substances 0.000 claims abstract description 17
- 239000011229 interlayer Substances 0.000 claims abstract description 5
- 239000000126 substance Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 23
- 229910052751 metal Inorganic materials 0.000 abstract description 13
- 239000002184 metal Substances 0.000 abstract description 13
- 229910052782 aluminium Inorganic materials 0.000 abstract description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- 239000004411 aluminium Substances 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 24
- 235000012239 silicon dioxide Nutrition 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 10
- 229920001721 polyimide Polymers 0.000 description 7
- 239000009719 polyimide resin Substances 0.000 description 7
- 239000000428 dust Substances 0.000 description 6
- 239000007888 film coating Substances 0.000 description 5
- 238000009501 film coating Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 239000007788 liquid Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- SCPYDCQAZCOKTP-UHFFFAOYSA-N silanol Chemical compound [SiH3]O SCPYDCQAZCOKTP-UHFFFAOYSA-N 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000005456 alcohol based solvent Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010791 quenching Methods 0.000 description 1
- 230000000171 quenching effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
(技術分野)
本発明は半導体装置に関し、特に多層配線構造の平坦化
された半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor device, and more particularly to a semiconductor device with a flattened multilayer wiring structure.
(従来技術)
半導体装置を平坦構造とする必要性は主に多層配線構造
における配線の断線防止のために生じており各種技術が
実用化されている。(Prior Art) The need for semiconductor devices to have a flat structure arises mainly to prevent wire breakage in multilayer wiring structures, and various techniques have been put into practical use.
その一つの技術に液化酸化膜を塗布する技術がある。こ
の技術は液状の二酸化7リコンを含む混合物をスピンコ
ードによりウェーハ上に塗布し、ベークすることにより
ウェーハ表面が残存した二酸化シリコン膜により平坦化
され、その上に形成される配線層の断線防止になる。One such technique is the technique of applying a liquefied oxide film. This technology uses a spin code to apply a mixture containing liquid 7-licon dioxide onto a wafer, and then bakes the wafer surface, which flattens the wafer surface with the remaining silicon dioxide film and prevents disconnections in the wiring layer formed on top of it. Become.
この方法は、他の方法のエンチバyり或はバイアススパ
ッタ法等に比べ簡便である利点がある。This method has the advantage of being simpler than other methods such as quenching or bias sputtering.
しかしながら、前記液状の二酸化シリコン膜を使う方法
では、以下に記す欠点がある。However, the method using the liquid silicon dioxide film has the following drawbacks.
(1)アルミニウムなどの配線層の上に直接シリコン皮
膜を形成した場合、配線層近傍の前記二酸化シリコン皮
膜が厚くなりすぎ、その結果クラックを生じ、上層配線
をショートし絶縁膜としての機能を失うという欠点があ
る。(1) When a silicon film is formed directly on a wiring layer such as aluminum, the silicon dioxide film near the wiring layer becomes too thick, resulting in cracks, shorting the upper layer wiring, and losing its function as an insulating film. There is a drawback.
(2)液状の二酸化シリコンより形成した二酸化シリコ
ン皮膜上にアルミニウム等の上層配線を被着する際に、
その被着条件を制限しなければ半導体装置の信頼度及び
生産性の低下を招くという問題が発生する。(2) When depositing upper layer wiring such as aluminum on a silicon dioxide film formed from liquid silicon dioxide,
Unless the deposition conditions are restricted, a problem arises in that the reliability and productivity of the semiconductor device are reduced.
例エバ、近年アルミニウムのエレクトロマイグレイジョ
ンに対する強さからスパッタ法による被着が用いられて
おり、この場合スルホール導通性を良くするため、アル
ミニウムスパッタ直前に半導体基板表面を逆スパツタを
行う必要があり、ヌスバッタするアルミニウムの段差に
対するカバレジ及びダレインサイズ等の膜質を均一に保
つため半導体基板を加熱する必要がある。For example, in recent years aluminum has been deposited by sputtering due to its strength against electromigration, and in this case, it is necessary to perform reverse sputtering on the semiconductor substrate surface immediately before aluminum sputtering to improve through-hole conductivity. , it is necessary to heat the semiconductor substrate in order to maintain uniform film quality such as coverage and duplex size for the step difference in aluminum that flops.
このようなプロセスを適用すると、液化酸化膜塗布法で
形成した二酸化シリコン皮膜からガス放出(主に水素ガ
ス)が起る。このためスパッタ装置内の真空度が低下し
、この状態でのスパッタアルミニウム膜は、エレクトロ
マ4クレイシミ/ステップカバレジ等半導体装置の品質
に悪影響を与えるので好ましくない。更にガス放出によ
り装置内の汚染がひどく、装置清掃頻度が多くなり生産
性の低下を招く。When such a process is applied, gas (mainly hydrogen gas) is released from the silicon dioxide film formed by the liquefied oxide film coating method. For this reason, the degree of vacuum in the sputtering apparatus decreases, and the sputtered aluminum film in this state is not preferable because it adversely affects the quality of the semiconductor device, such as electromer 4 crease stains and step coverage. Furthermore, the gas release causes severe contamination within the device, which increases the frequency of cleaning the device, resulting in a decrease in productivity.
(3)液化酸化膜塗布法は、通常アルコール系溶媒とシ
ラノール等の混合液をスピンコ−) Ll、400〜4
50’Cの温度でベータすることにより二酸化シリコン
皮膜を形成するが、該液化酸化膜混合液の成分は90%
以上がアルコール系溶媒であるため乾燥し易く、該シラ
ノール等がゴミの発生源となるので塗布装置を含めその
取扱いには充分注意が必要であるという等の問題点があ
った。(3) In the liquefied oxide film coating method, a mixture of an alcohol solvent and silanol, etc. is usually spin coated) Ll, 400-4
A silicon dioxide film is formed by betaening at a temperature of 50'C, and the composition of the liquefied oxide film mixture is 90%.
Since the above solvents are alcohol-based solvents, they tend to dry easily, and the silanol and the like become a source of dust, so there are problems in that sufficient care must be taken when handling them, including the coating equipment.
(発明の目的)
本発明の目的は、ゴミの発生による品質及び歩留り低下
の問題がなく、平坦度の良い、しかも生産性の優れた多
層配線構造を持つ半導体装置を提供するにある。(Objective of the Invention) An object of the present invention is to provide a semiconductor device having a multilayer interconnection structure which is free from the problem of deterioration in quality and yield due to the generation of dust, has good flatness, and has excellent productivity.
(発明の構成)
本発明の半導体装置は、多層配線構造を有する半導体装
置において、前記多層配線構造を形成する層間絶縁膜が
第1の絶縁皮膜と、該第1の絶縁皮膜上に形成された表
面平坦化性の優れた第2の絶縁膜と、該第2の絶縁膜上
に形成された第3の絶縁膜の3層構造であることにより
構成される。(Structure of the Invention) A semiconductor device of the present invention is a semiconductor device having a multilayer wiring structure, wherein an interlayer insulating film forming the multilayer wiring structure is formed on a first insulating film and the first insulating film. It has a three-layer structure including a second insulating film with excellent surface flattening properties and a third insulating film formed on the second insulating film.
(実施例)
以下、本発明の実施例につき、図面を参照して説明する
。(Example) Examples of the present invention will be described below with reference to the drawings.
第1図は本発明の第1の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the invention.
第1図において、lは不純物のイオン注入又は拡散その
他の工程を経過したあと各種要素を形成したシリコン基
板であり、2はシリコン基板表向に形成された絶縁膜、
例えばシリコン酸化膜でありシリコン基板lを保獲し、
又その反転を防止するに足る厚gt−有している。3は
アルミニウムなどの配線用金属である。また、4はCV
D成長法、プラズマ法等により形成された第1の絶縁
膜であり、該絶縁膜の厚さは500A以上あれば良い。In FIG. 1, 1 is a silicon substrate on which various elements have been formed after ion implantation or diffusion of impurities and other processes, 2 is an insulating film formed on the surface of the silicon substrate,
For example, it is a silicon oxide film that captures the silicon substrate l,
It also has a thickness gt-sufficient to prevent its inversion. 3 is a wiring metal such as aluminum. Also, 4 is CV
The first insulating film is formed by a D growth method, a plasma method, etc., and the thickness of the insulating film may be 500A or more.
5は液化酸化膜である第2の絶縁膜、6は4と同じくC
VD成長法等による第3の絶縁膜、7は第3の絶縁膜上
に形成された上層配線である。5 is a second insulating film which is a liquefied oxide film, and 6 is C like 4.
A third insulating film 7 is formed by VD growth or the like, and 7 is an upper layer wiring formed on the third insulating film.
本実施例では金属配線3を核う層間絶縁膜は液化酸化膜
の単層ではなく第1の絶縁膜4.第2の絶縁膜8.第3
の絶縁膜603層膜で構成され、しかも平坦化効果の大
きい第2の絶縁膜8が2つの絶縁膜に挾まれた構造とな
っている。In this embodiment, the interlayer insulating film enclosing the metal wiring 3 is not a single layer of liquefied oxide film but a first insulating film 4. Second insulating film 8. Third
The second insulating film 8, which has a large planarizing effect, is sandwiched between two insulating films.
すなわち、下層金属配線3には直接液化酸化膜が付着さ
れることがなく第1の絶縁膜4が形成されているので直
接液化酸化膜を付着はせたときのように下層金属配線の
ところで液化酸化膜がj〒くなりクラックを生じ、それ
による絶縁不良やノヨート現象の原因とならない。That is, since the first insulating film 4 is formed without directly attaching the liquefied oxide film to the lower metal wiring 3, the liquefied oxide film does not liquefy at the lower metal wiring, unlike when the liquefied oxide film is directly attached. This prevents the oxide film from becoming thick and causing cracks, which will cause poor insulation and the porosity phenomenon.
また液化酸化膜8の上には第3の絶縁膜が液化酸化膜を
覆って形成されているためその後のプロセスで液化酸化
膜塗布法で形成された二酸化シリコン皮膜からのガス放
出等を少なくすることができる。また液化酸化膜塗布法
で形成された二酸化シリコン皮膜からのゴミの発生を小
さくおさえることができる。Furthermore, since a third insulating film is formed on the liquefied oxide film 8 to cover the liquefied oxide film, gas release from the silicon dioxide film formed by the liquefied oxide film coating method in subsequent processes is reduced. be able to. Further, the generation of dust from the silicon dioxide film formed by the liquefied oxide film coating method can be suppressed.
第2図は本発明の他の実施例の断面図である。FIG. 2 is a sectional view of another embodiment of the invention.
第2図に示す実施例の構成は第1の実施例と同じである
が、異なる点は本発明の3層構造の中間に位置する表面
平坦化性の優れた第2の絶縁膜6が液化酸化膜塗布法に
よる二酸化シリコン酸化膜でなく有機性物質からなる絶
縁膜であることである。The structure of the embodiment shown in FIG. 2 is the same as the first embodiment, but the difference is that the second insulating film 6 with excellent surface flattening properties located in the middle of the three-layer structure of the present invention is liquefied. The insulating film is not a silicon dioxide film formed by an oxide film coating method, but is made of an organic substance.
第1の実施例と同様にして、シリコン基板1上にはシリ
コン酸化膜2.下層金属配線3.第1の絶縁膜4が形成
される。次いで、有機性絶縁物であるポリイミド樹脂5
が第1の絶縁膜4上にスピンコードにより塗布され、ベ
ータすることにより平坦化された緻密な膜が形成される
。ポリイミド樹脂は揮発性がすくなく緻密質のためゴミ
発生の問題は起らない。Similarly to the first embodiment, a silicon oxide film 2. Lower layer metal wiring 3. A first insulating film 4 is formed. Next, polyimide resin 5 which is an organic insulator
is coated on the first insulating film 4 using a spin code and beta-coated to form a planarized and dense film. Polyimide resin has low volatility and is dense, so there is no problem of dust generation.
また6はポリイミド樹脂上に形成された第3の絶縁膜で
あり、ポリイミド樹脂膜を保護しその後のプロセスを安
定化することができる。7は本実施例の3層層間絶縁膜
上に形成された上層金属配線であり、必要により上層金
属配線止金下層配線の場合と同様に第1の絶縁膜4及び
ポリイミド樹脂5を形成してもよく、更に必要によりポ
リイミド樹脂5上に絶縁膜を形成してもよい。Further, 6 is a third insulating film formed on the polyimide resin, which can protect the polyimide resin film and stabilize subsequent processes. Reference numeral 7 indicates an upper layer metal wiring formed on the three-layer interlayer insulating film of this embodiment, and if necessary, a first insulating film 4 and a polyimide resin 5 are formed as in the case of the upper layer metal wiring holder and the lower layer wiring. Furthermore, an insulating film may be formed on the polyimide resin 5 if necessary.
以上説明したとおり、本発明の第2の実施例によ11ば
、第1の実施例の場合より絶縁性、平坦化が進み、ガス
やゴミの発生のすくない多層配線構造を有する半導体装
置が得られる。As explained above, according to the second embodiment of the present invention, it is possible to obtain a semiconductor device having a multilayer wiring structure that has better insulation and flatness than the first embodiment, and is less likely to generate gas or dust. It will be done.
なお第1.第3の絶縁膜としては酸化シリコン膜、窒化
シリコン膜が一般的に使用されるがアルミナ膜も使用で
きる。なお第1と第3の絶縁膜は同じ種類のものでも、
また異種のものでもよく必要条件により選択できる。Note that the first thing. As the third insulating film, a silicon oxide film or a silicon nitride film is generally used, but an alumina film can also be used. Note that even if the first and third insulating films are of the same type,
In addition, different types may be used and can be selected depending on the necessary conditions.
ただし同じ種類のものであれば生産設備、工程を簡易化
することができる。However, if they are of the same type, production equipment and processes can be simplified.
(発明の効果)
以上説明したとおり、本発明によれば、従来例の如く、
ゴミの発生やガス放出による品質、歩留り低下の問題が
なく、平坦度のよい電気特性が優れ多層配線構造を持つ
半導体装置が得られ、且つ通常の製造設備により生産で
きるという生産性に優れているという効果も得られる。(Effect of the invention) As explained above, according to the present invention, like the conventional example,
There is no problem of quality or yield deterioration due to generation of dust or gas emission, semiconductor devices with good flatness, excellent electrical properties, and multilayer wiring structure can be obtained, and they are highly productive as they can be produced using normal manufacturing equipment. This effect can also be obtained.
第1図、第2図は本発明の実施例の断面図である。
l・・・・・・半導体シリコン基板、2・・・・・・シ
リコン酸化膜、3・・・・・・金属配線(下層)、4・
・・・・・絶縁膜、5・・・・・・ポリイミド樹脂、6
・・・・・・絶縁膜、7・・・・・・金属配線(上層)
、8・・・・・・液化酸化膜。
第1頂
を201 and 2 are cross-sectional views of embodiments of the present invention. l...Semiconductor silicon substrate, 2...Silicon oxide film, 3...Metal wiring (lower layer), 4...
...Insulating film, 5...Polyimide resin, 6
...Insulating film, 7...Metal wiring (upper layer)
, 8...Liquid oxide film. 1st peak 20
Claims (4)
多層配線構造を形成する層間絶縁膜が第1の絶縁被膜と
、該第1の絶縁被膜上に形成された表面平坦化性の優れ
た第2の絶縁膜と、該第2の絶縁膜上に形成された第3
の絶縁膜の3層構造よりなることを特徴とする半導体装
置。(1) In a semiconductor device having a multilayer wiring structure, an interlayer insulating film forming the multilayer wiring structure includes a first insulating film and a second insulating film having excellent surface flattening properties formed on the first insulating film. an insulating film formed on the second insulating film, and a third insulating film formed on the second insulating film.
A semiconductor device comprising a three-layer structure of insulating films.
からなる絶縁膜である特許請求の範囲第(1)項記載の
半導体装置。(2) The semiconductor device according to claim (1), wherein the second insulating film having excellent surface flattening properties is an insulating film made of an organic substance.
特許請求の範囲第(1)項又は第(2)項記載の半導体
装置。(3) The semiconductor device according to claim (1) or (2), wherein the first and third insulating films are of the same type.
膜である特許請求の範囲第(1)項又は第(2)項記載
の半導体装置。(4) The semiconductor device according to claim (1) or (2), wherein the first and third insulating films are different types of insulating films.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24031083A JPS60132344A (en) | 1983-12-20 | 1983-12-20 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24031083A JPS60132344A (en) | 1983-12-20 | 1983-12-20 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60132344A true JPS60132344A (en) | 1985-07-15 |
Family
ID=17057551
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24031083A Pending JPS60132344A (en) | 1983-12-20 | 1983-12-20 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60132344A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1987002828A1 (en) * | 1985-11-04 | 1987-05-07 | Motorola, Inc. | Glass intermetal dielectric |
US4774561A (en) * | 1985-05-23 | 1988-09-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
JPH0362554A (en) * | 1990-08-06 | 1991-03-18 | Fuji Xerox Co Ltd | Semiconductor device and manufacture thereof |
JPH04167429A (en) * | 1990-10-30 | 1992-06-15 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
EP0681325A2 (en) * | 1994-04-28 | 1995-11-08 | Xerox Corporation | Thin-film structure with insulating and smoothing layers between crossing conductive lines |
US5486939A (en) * | 1994-04-28 | 1996-01-23 | Xerox Corporation | Thin-film structure with insulating and smoothing layers between crossing conductive lines |
-
1983
- 1983-12-20 JP JP24031083A patent/JPS60132344A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4774561A (en) * | 1985-05-23 | 1988-09-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
WO1987002828A1 (en) * | 1985-11-04 | 1987-05-07 | Motorola, Inc. | Glass intermetal dielectric |
JPH0362554A (en) * | 1990-08-06 | 1991-03-18 | Fuji Xerox Co Ltd | Semiconductor device and manufacture thereof |
JPH04167429A (en) * | 1990-10-30 | 1992-06-15 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
EP0681325A2 (en) * | 1994-04-28 | 1995-11-08 | Xerox Corporation | Thin-film structure with insulating and smoothing layers between crossing conductive lines |
US5486939A (en) * | 1994-04-28 | 1996-01-23 | Xerox Corporation | Thin-film structure with insulating and smoothing layers between crossing conductive lines |
EP0681325A3 (en) * | 1994-04-28 | 1997-04-23 | Xerox Corp | Thin-film structure with insulating and smoothing layers between crossing conductive lines. |
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