JPS60127477A - Logical circuit - Google Patents

Abstract

PURPOSE:To make it possible to hold a node to arbitrary potential and to enable the confirmation of the state thereof from the outside by simple constitution, by selectively fusing the fuses inserted between P-ch MOSFET, N-ch MOSFET and a power source. CONSTITUTION:When fuses 26, 29 are under a continuity state, a power source Vcc is applied to the gate of P-ch MOSFET21 as it is and the FET21 is turned OFF. The potential of the power source Vcc is applied to the gate of N-ch MOSFET24 and FET24 is also turned OFF. Therefore, the signal applied to an input terminal 23a is transmitted to an output terminal 23b as it is. For example, when the fuse 26 is fused, earth potential is applied to the gate of FET21 through a high resistor 27 and FET21 is turned ON while a node 23 comes to the potential of the power source Vcc and the signal imparted to the terminal 23a is neglected to always output the potential of the power source Vcc to the terminal 23b. When the fuse 29 is fused, similar operation is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Substances of the Invention] The present invention relates to a logic circuit that can fix and hold a specific signal line at an arbitrary logic level and that can check this state from the outside.

[Technical background of invention]

For example, in a complementary tJ o s (hereinafter abbreviated as C-14O8) static type access memory, addresses and memory cells correspond to each other, so in a device with 2n memory cells, n address lines An arbitrary memory cell is specified by introducing each logical value.

By the way, in a C-MOS static random access memory having 2n memory cells, if even one memory cell is defective, the chip itself naturally becomes a defective product and has no product value at all.

However, here, the above-mentioned defective memory cells are not included.
If it is a C-UOS static random access memory consisting of 1 memory cell, it has sufficient product value. In such a case, one specific address line may be fixed to logic 1H'' or 1L''. Therefore, for products that can be used by such means, for example, a predetermined mark may be attached, and the logic value of the address line designated by the user may be fixed by this mark. However, for this purpose, if the address line whose logical value is to be fixed is left in a floating state, there is a possibility that an incorrect address will be selected, so it is necessary to forcibly fix the logical value to a predetermined logical value.

Incidentally, the address input circuit of a C-MOS static random access memory uses, for example, an inverter circuit as shown in FIG. 1 or a NOR circuit as shown in FIG. 2.

That is, in the inverter circuit shown in FIG.
JO8) The source of transistor T is a positive voltage, 4 va
C and its drain is connected to the drain of an N-channel MO8 transistor T2. Furthermore, this N channel),
(OS) The source of the transistor T2 is grounded, the gates of the transistors T, , T, and the like are commonly connected to form the input terminal 11, and the commonly connected drains are the output terminal 12.
I am trying to get an inverted output as follows.

In addition, as shown in Fig. 2, the source of a P-channel MO3 transistor T is connected to the lE power supply V○0, the drain is connected to the source of an N-channel IJO8) transistor T4, and the drain is connected to an N-channel MO3 transistor T4. '
Connect to the drain of r, +'r6. Furthermore, the sources of these N-channel transistors T, , T, 1708) are grounded. And the above P-channel transistor 'r,
The gates of the transistor T6 (N channel M OS) are connected in common, the common connection point of the gates is the input terminal 13, and the gates of the transistor T3 (N channel) J OS) are connected in common. The point is set as the signal input terminal 14 of 7i11. The valley drains of the P-channel IvIO8) transistor 'I'4 and the N-channel M08 transistors T and IT are commonly connected to the output terminal I5.

Therefore, if the output of such an inverter circuit or NOR circuit can be fixed to an arbitrary logical value,
For example, if one memory cell in a C-1 JO static random access memory is inactive, it can be used as a good C-1 JOB static random access memory consisting of half of the memory cells.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a logic circuit that can fix and hold any signal line at any logic level and check this state from the outside. That is.

[Summary of the invention]

That is, in the present invention, a P-channel MO8) transistor and a resistor are inserted in series between the first power supply and the signal line, and a resistor and an N-channel MO1.40E3 transistor are inserted between this signal and the second power supply.
) A transistor is inserted in series, - the above P-channel MOS
The gate of the transistor and the 10th and 11th sources and the above N
This method is characterized in that fuse elements inserted between the gates of the channel MOS transistors and the second power source are selectively blown out.

[Examples of actual rights to inventions]

Hereinafter, a first embodiment of the present invention will be explained in detail with reference to the circuit diagram shown in FIG. P channel UOS transistor 2I
The drain of is connected to the first power supply, i.e.
K connection, and the source is connected to the node 23 via the resistor 22. and connect the source of the transistor 24 (channel MO8) to the second power supply, that is, to the ground 'N,
The drain is connected to node 23 via resistor 25. A first fuse 26 is interposed between the first electric voltage Vcc and the gate of the P-channel VOS transistor 2Z, and a high resistance 27 is interposed between this gate and the second power supply. Also N channel) 70S) transistor 24
The gate of the first power supply r (connected through the high resistance 28,
This gate is connected to a second power source via a second fuse 29. Furthermore, the input terminals 23a1 and 23a1 are connected to the output terminals 23a1 and 23a1 and the terminals 2 and 2 are connected to both ends of the -domain 23, respectively. l).

With this configuration, each of the first and second fuses 2
When 6.29 is fully passed, the first power supply Vaa is directly applied to the gate of the P-channel IJO8) transistor 21, so the transistor 2I is turned off. Further, the gate of the N-channel +J OS transistor 24 has a second
The state of the power supply is applied, and the transistor 24 is also turned off.

Therefore, the signal applied to the input terminal 23a is output as is from the output terminal 23b. Further, in this case, the current flowing through each of the high resistances 27 and 28 is extremely small.

If the first fuse 26 is blown, a high resistance 27 is applied to the gate of the P-channel IJO8) transistor 2I.
A ground potential is applied through the transistor 2I, and the transistor 2I is turned on. Therefore, the first power supply VaO of nodes 2 and 9
The potential of the first power supply Vcc is always output at the output terminal 2.9blC1'i, ignoring the signal applied to the input terminal 23a.

When the broken second fuse 29 is blown, the voltage of the first stirrup voltage Vca is applied to the gate of the N-channel + AOS transistor 24 through the high resistance 28, and the transistor 24 (Ii Therefore, )-do23
is 'X17 of ti:b2, which becomes the t position of the source, that is, the ground potential, and the signal applied to the human power sensor M element 23a is ignored, and the ground level 1i; is always outputted to the output terminal 23b.

In addition, when the fuse 26 in step 1 is blown, if the input terminal 23a is connected to the voltage level IIL, it is possible to detect the negative current, that is, the blL leakage current.
If the fuse 29 is blown, the input terminal 23a is
It is possible to detect the potential of the power supply VCC and the old power 1, that is, the inflow current. Therefore, the blown fuse can be known from the outside from the voltage level applied to the input terminal 2.9a and the direction in which the current flows at that time.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a logic circuit in which a node can be held at an arbitrary position of -111 with an f''A configuration, and its state can be checked from the outside.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of an inverter, FIG. 2 is a diagram showing an example of a NOR circuit, and FIG. 3 is a circuit diagram showing a sister example of the present invention.

Claims (1)

[Claims] (1) A P-channel MO inserted in series between the first power supply and the node from which the input terminal and output terminal are derived8) A transistor and a resistor inserted in series between this node and the second power supply. resistor and N-channel qO8) transistor, the first power supply and the P-channel! 408) A fuse element interposed between the gate of the transistor and holding the node at the potential of the @l power supply when blown out; and the P-channel IAOS; a fuse element which is inserted between the second power supply and the gate of the N-channel MO transistor and holds the node at the potential of the second power supply when blown; S) A logic circuit comprising a high resistance inserted between the gate of the transistor and a first power source.