JPS6012180Y2 - data logger - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a data logger, and an object of the present invention is to provide a highly accurate data logger that eliminates the influence of common mode voltage caused by stray capacitance between a guard and a case.

FIG. 1 is a block diagram of an example of a conventional data logger.

In addition, the figure illustrates the case where a thermocouple is used as a sensor, and only one channel is shown as the number of channels.

In Figure 1, IH9IL is an input terminal, RLc, R
Lo is a scanner relay for each channel, RL
M is a master relay, AMP is an amplifier, A/D is an analog/digital converter, G is a guard, ■ is a power supply, K is a case, TC is a thermocouple, and CL is a cold junction compensation circuit.

Thermocouple TC is terminal ■.

9 Connected to IL, this terminal, I)l? IL is connected to a master relay RL via a scanner relay RLo, and the master relay RL44 is connected to an analog-to-digital converter A/D via an amplifier AMP.

Guard G is arranged so as to surround an analog circuit including an amplifier AMP and an analog-to-digital converter A/D,
One end is the scanner relay RLo and the master relay RL.
It is connected to the L (row) side connection line between the M and M.

AMP, A/D, G, etc. are arranged inside the case.

A power supply (2) is a power supply for the data logger body, and is placed outside the guard G, and its negative electrode side is grounded together with the case.

The cold junction compensation circuit CL is made up of a constant current groove gI and a bridge BR having a temperature sensing element on one side, and the positive terminal side of the power supply (2) is connected to the relay RLc via the cold junction compensation circuit CL.

It is connected between relay RLo and master relay RLM.

Insulation resistance and stray capacitance exist between the guard G and the case.

The insulation resistance is indicated by Ro and the stray capacitance Co is indicated.

In such a data logger, as shown by the timing chart in Fig. 3A, first the relay RLc is turned on and the output of the cold junction compensation circuit CL is amplified by the amplifier AMP via the master relay R14A. A converter A/D converts it into a digital signal.

In this case, the cold junction compensation circuit CL is the outguard power supply ■
As a result, when the output of the cold junction compensation circuit CL is applied to the amplifier AMP, the stray capacitance Go is charged with the output of the power supply V and becomes a common mode voltage.

According to an example of an experiment, the stray capacitance Co is about 1500 PF, and the insulation resistance Ro is several 100 to several 1000 MΩ.
That's about it.

As a result, the time constant of RoCo is large, and the charges accumulated in Co are not easily discharged.

In the device shown in Fig. 1, the relay R is as shown in Fig. 3 A.
After turning off Lc, turn on relay RL after a predetermined time.
o is turned on, the output of the thermocouple TC is amplified by the amplifier AMP, and then converted into a digital signal by the A/D.

In this case, there is an impedance between the tip of the thermocouple TC and the ground, but when that impedance is tossed to R1, the electric charge charged in the stray capacitance Co while the relay RLo is on is as shown by the dotted line in the figure. This impedance R1
discharge through.

This discharge current causes a voltage drop in the ground impedance R1, and this voltage drop is added to the output of the thermocouple in normal mode, which is amplified by the amplifier AMP and then converted to a digital signal, which is then sent to the processor (not shown), etc. is given and processed.

Therefore, this normal mode voltage appears as an error.

The above is a notable example, but in general, when scanning channel relays RLc and RLo, the common mode voltage of the channel is added to the stray capacitance Co.
If the value of this common mode voltage is significantly different from the common mode voltage of the previous channel, a charging (or discharging) current will flow through the signal line at the same time as the channel is switched by this capacitor CO.

A voltage drop between the current during charging (discharging) and the impedance of the signal line is applied to the signal source in normal mode, resulting in an error.

The present invention has been devised in view of these points, and is intended to eliminate the influence of the common mode voltage as described above.

FIG. 2 is a block diagram showing the main parts of an embodiment of the data logger of the present invention.

In FIG. 2, the same reference numerals as in FIG. 1 are used to omit their redescription.

In FIG. 2, R is a current limiting resistor, SW is a switch, and the resistor R and switch SW are connected in series between the guard G and the case.

As a switch SW, a relay, transistor or F
A voltage proof type such as ET is used.

In the data logger having such a configuration, the charge accumulated in the stray capacitance Co is discharged by turning on the switch at the timing when the scanner relays RLc, RLo, . . . are switched.

For example, as shown in Figure 3, scanner relays RLc and R
If you turn on the switch SW only when switching Lo,
The charge accumulated in Co during measurement of the cold junction temperature is discharged.

In addition, as shown in Figure 3, by turning on the switch SW when switching each scanner relay, the influence of the cold junction temperature and the common mode voltage of all measurement channels can be reduced by the stray capacitance Co when all relays are switched. is removed by discharging the charge.

As explained above, according to the present invention, a current limiting resistor and a switch are provided in series between the guard and the case, and by turning on this switch when switching the relay, the common mode voltage due to the stray capacitance between the guard and the case can be reduced. As a result, a highly accurate data logger can be obtained.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the main parts of a conventional data logger;
The figure is a block diagram of the main parts of the data logger of the present invention, and FIG. 3 is a diagram for explaining the operation of the data logger of the present invention. RLc, RLo...Scanner, A/D...Song analog-to-digital converter, G...Guard,
K・Curve・Case, R・・・・Current limiting resistor, SW・
·····switch.

Claims (1)

[Scope of utility model registration request] In a data logger that inputs multi-channel input via a scanner relay to an analog-to-digital converter surrounded by a guard, a current limiting resistor and the scanner relay are connected between the case of the data logger and the guard. Data logger 0 is made by connecting switches in series that turn on when the switch is switched on.