JPS6011813B2 - semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory diamond layer, and in particular to a semiconductor memory layer (MIS).
One transistor (TRS) consisting of a capacitive element and a switching MISFET (insulated gate turtle field effect transistor)
) type memory cells.

The ITRS type memory cell is composed of an S capacitive element as a storage means and a MISFET as a switching means for penetrating and reading.

Since this memory cell is constructed from a semiconductor integrated circuit, it is desirable to reduce the area occupied by the memory cell and improve the degree of integration. Therefore, it is an object of the present invention to provide a semiconductor memory device in which the cell area of an ITRS type memory cell is reduced by 4.0 mm, thereby improving the number of memory cells.

The basic structure of the present invention for achieving the above object is as follows:
facing each other so as to sandwich a semiconductor region exhibiting a second conductivity type opposite to the first conduction fin type selectively formed on the inner surface of the semiconductor having a conduction turtle type, and spaced apart from the semiconductor region; a first conductive layer formed on the semiconductor, at least a part of which serves as one electrode in the capacitive element, a first conductive layer formed on the semiconductor region, and a first conductive layer formed on the semiconductor region; , formed on the semiconductor between the second capacitive elements, at least a part of which is connected to the first and second switching MI
and a second conductor layer used as a gate electrode of the SFET, and the first conductor layer and the second conductor fin layer are insulated from each other and at least partially overlap each other. It is characterized by the fact that

Hereinafter, the present invention will be specifically explained with reference to the drawings along with examples.

FIGS. 1A to 1E and FIGS. 2A and 2B are cross-sectional views of manufacturing steps for explaining an example of the present invention.

In the present invention, in order to reduce the cell area of the ITRS type memory cell, a MISFET using the coupling principle of a CCD (charge coupled device) is used as a switching element. Specifically, a memory cell is formed by the manufacturing process shown in the figure. [a-n-type semiconductor substrate 1
A Si02 film 2 serving as a field insulating film is formed thereon.
'b - Selectively remove the Si02 film 2 on the semiconductor region where the switching skin SFET and MIS capacitive element are to be formed, and then thin Si02 film 2 which will become the gate insulating film.
′ is formed.

'c} Of the upper Si02 film 2', the Si02 film 2' on a common region of switching MISFETs formed facing each other, for example, a semiconductor region where a common source (region to be connected to a bit line) is to be formed. selectively remove.

A 'd' polycrystalline silicon layer 3 is selectively formed on the surface of the substrate at the portions that are to become the gate electrodes and bit lines of the MIS capacitor.

At this time, the polycrystalline silicon layer 3 to become the bit line
is directly connected to the surface of the substrate 1 in the portion that is to become the source region of the switching MISFET.
[c} A semiconductor impurity (for example, boron) is deposited to make the polycrystalline silicon layer 3 conductive.

Next, by heat treatment, the source region 4 of the MISFET is diffused and an insulating polycrystalline silicon thermal oxide film 3'' is formed on the surface of the conductive polycrystalline silicon 3'. As shown, the gate electrode 5 of the MISFET made of the same guiding fin polycrystalline silicon layer is overlapped with the gate electrode 3' and source region 4 of the MIS capacitive element via the polycrystalline silicon thermal oxide film 3''. selectively formed.

Next, an aluminum wiring line constituting a word line is formed so as to be connected to the MISFET gate, and a patchy G film for surface protection is formed (not shown). Note that this figure shows a cross-sectional view of a memory cell for 2 bits. In the ITRS type memory cell described above, a predetermined power supply voltage is always applied to the gate electrode constituting the skin S capacitive element, and the semiconductor region directly under the gate electrode is made into a depletion layer.

Therefore, even if one region of the switching SFET, for example, the drain (region to be connected to the MIS capacitor) is omitted as in the present invention, the distance between the gate electrode of the skin S capacitor and the gate electrode of the MISFET is Since the distance between the two gate electrodes is only about 1000 to 2000 A, which is the thickness of the insulating film, the spread of the depletion layer by both gate electrodes overlaps with each other, so carriers can be transferred even without the drain region, and the switching element It acts as.

This can be easily understood from the fact that it is similar to the operating principle of a CCD (charge coupled device). That is,
According to the present invention, the function as a memory cell can be easily provided by controlling the thickness of the insulating film. From the above, the memory cell pattern according to the present invention has the gate electrode of the MIS capacitive element and the skin SFET.
Since the gate electrodes are formed in separate steps, as shown in FIG. 3, these gate electrodes can be overlapped and the drain region of the switching MISFET can be omitted.

Therefore, in a conventional memory cell in which the gate electrode 3' of the skin S capacitor element and the gate electrode 5 of the MISFET are formed by patterning a single conductive polycrystalline silicon layer as shown in FIG. In comparison, the area it occupies can be reduced as much as 4 times. In FIG. 3, 6 is a word line made of aluminum wiring, and C, C2 are connection points between the word line and the gate fin pole of the MISFET. Further, in FIG. 4, the bit line is made up of a diffusion layer, whereas, as shown in FIG. 3, the bit line according to the present invention is made up of a conductive polycrystalline silicon layer. Therefore, the parasitic capacitance of the bit line can be reduced, so that the output detection level AV can be increased as is clear from the following equation '1'. △V=;
Zenzo Q...'·1 Here, Cs is the capacitance value of the MIS capacitive element, Co is the capacitance value of the parasitic capacitance of the bit line, and Q is the amount of accumulated charge.

As a result, the number of memory cells that can be connected to one bit line can be increased, so that together with the above-described improvement in the degree of integration, a large storage capacity can be achieved. In the above structure, since the polycrystalline silicon 3' is formed on and in contact with the source region 4, the depth of the source region 4 itself can be easily reduced.

By reducing the depth of the source region 4, the junction area between the source region 4 and the semiconductor substrate 1 can be reduced, and the junction capacitance can be reduced. As a result, the detection level ΔV can be increased similarly to the above. The invention is not limited to the embodiments described above, but can explore various embodiments.

For example, an aluminum vapor deposition layer may be used as the electrode of the MISFET.

Further, the bit line may be formed by a diffusion layer, but
In this case, care must be taken that the parasitic capacitance increases as explained above. Furthermore, in FIG. 3, the word line 6 may be formed of a conductive polycrystalline silicon layer in the vertical direction, and the bit line 3' may be formed of aluminum wiring in the vertical direction.

Furthermore, it goes without saying that the MISFET may be an n-channel MISFET.

[Brief explanation of the drawing]

1A to 2E and 2 show an example of a cross-sectional view of the manufacturing process of a semiconductor memory rhombus according to the present invention, FIG. 3 shows a plan view thereof, and FIG. 4 shows a conventional ITRS type memory cell. 1 shows an example of a plan view of. 1...Substrate, 2,2'...Si○ is huge, 0
...Polycrystalline silicon layer, 3'...Conductive polycrystalline silicon layer, 3''...Polycrystalline silicon thermal oxide film, 4...Source, 4' ··…·drain,
5...Gate electrode (conductive polycrystalline silicon layer)
, 6...word line (aluminum wiring layer). Figure 4 Figure 1 Figure 2 Figure 3

Claims (1)

[Scope of Claims] 1. A semiconductor region having a second conductivity type opposite to the first conductivity type selectively formed on the inner surface of the semiconductor having the first conductivity type, and a semiconductor region on the semiconductor region in contact therewith. first and second capacitive element forming regions, which are formed to face each other so as to sandwich the first conductor layer formed in the above manner and the semiconductor region, and to be spaced apart from the semiconductor region; and at least one of the first and second capacitive element forming regions. a second conductive layer formed on the semiconductor as one electrode of a capacitive element formed in the capacitive element forming region, and between the semiconductor region and the first and second capacitive element forming regions; a third conductive layer formed on the semiconductor, at least a part of which is used as a gate electrode of the first and second switching MISFETs; A semiconductor memory device characterized in that the body layers are insulated from each other and at least a portion thereof overlaps each other. 2. A fourth conductive layer is further connected to the third conductive layer, and the fourth conductive layer extends over the second conductive layer while being insulated from it. A semiconductor memory device according to claim 1.