JPS60111289A - Refresh memory write control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] This invention relates to a refresh memory write control method for a display device having a refresh memory [Prior art and its problems] This type of refresh memory write control method is used. As a conventional display device, the one shown in FIG. 1 is known. That is, in FIG. 1, l is a CRT display device, which is composed of a display control section 2 and a display section 3. As shown in FIG.

The display control unit 2 is composed of an arithmetic processing unit connected to an external processing unit such as a computer via a common bus 4, and receives display information sent from the external processing unit, and based on this display information ← address data. , character pattern code, and the like to the display section 3 via the common bus 4, and outputs a predetermined write control signal to the display section 3.

The display section 3 includes a refresh memory 5 that stores the character pattern code sent from the display control section 2, and a timing control section 6 that controls the readout address of the refresh memory 5 in synchronization with the scanning of the CRT display 9, which will be described later. , a character generator 7 that converts the character pattern code output from the refresh memory 5 for 80 hours into pattern data to be displayed on the CRT display 9, and a video control unit that converts the pattern data output from the character generator 7 into a video signal. 8, and a CRT display 9 to which video signals output from the video control section 8 are supplied.

Here, the refresh memory 5 has a memory capacity that corresponds one-to-one with pixels or characters constituting one screen of the CRT display 9, and each memory address indicates the type of character pattern of a certain size. The code, ie, the character code, is stored as the screen content.

By the way, in the write control method of the CRT character display device 1 having the above configuration, the size of the basic pattern that can be displayed with the character pattern code stored in each memory address of the refresh memory 5 is, for example, , is fixed to 8x8 dots. Therefore, when displaying an enlarged pattern of 16x16 dots, which is twice the size of this basic pattern, for example, the Roman alphabet rAJ
For example, as shown in Figure 2 (a) to (d), 4
Character pattern codes corresponding to the character patterns are prepared and stored in the refresh memory 5 in a predetermined order as shown in FIG. 3 (al).

As a result, the enlarged character pattern P is displayed on the CRT display 9, as shown in FIG. 3 fb).

However, in such a conventional refresh memory write control method, when writing a character pattern code to the refresh memory by the display control unit 2, depending on the pattern size to be displayed,
The display control unit 2 stores the write address in the glue fresh memory 5 for each basic pattern constituting the pattern.
The arithmetic processing must be performed on the arithmetic processing unit side constituting the display control section 2, which increases the burden on the processing program of the display control section 2 and causes problems such as a reduction in the display processing speed.

[Purpose of the invention]

When displaying a pattern of a size different from the basic pattern, this invention automatically sets and writes the address position for each basic pattern glue fresh memory constituting the enlarged pattern, so that the display controller side It is an object of the present invention to provide a refresh memory write control method that can reduce the burden and display enlarged patterns at high speed, thereby solving the problems of the conventional device.

[Key points of the invention]

The present invention includes a control device that controls an address register that specifies a write address of a refresh memory in which a character pattern code is written so that the write address is changed in a predetermined order every time a character pattern code is written to the refresh memory. This makes it possible to display patterns other than the basic pattern at high speed while reducing the burden on the display control section.

[Embodiments of the invention]

Embodiments of the present invention will be described below based on the drawings.

FIG. 4 is a process diagram showing one embodiment of the present invention. In FIG. 4, a refresh memory 5 and a refresh memory write control device 10 are connected to a display control section 2 via a common bus 4. In FIG.

The refresh memory write control device 10 includes an X address register 12, an X address register 13, a pattern size setting register 14, a counter 15, and a control circuit 16.

The X address register 12 and the Y address register 13 are each connected to the display control section 2 via a common lotus 4, and address data sent from the display control section 2 is written therein, and address data output from the display control section 2 is written therein. Each time a delay signal SD obtained by delaying the write control signal SR of the refresh memory 5 by a predetermined time by the delay circuit 17 is supplied, the address control section ? The setting contents are incremented or decremented by 1asAx and SAY.

The pattern size setting register 1 - 4 is connected to the display control section 2 via the common bus 4 , and the pattern size data indicating the pattern size sent from the display control section 2 is received as a write control signal from the display control section 2 . Written by SW.

The counter 15 receives the write control signal SW from the display control section 2 or the control signal SC from the control circuit 16 and the delay signal SD from the delay circuit 17 at its clear terminal.
It is cleared every time the AND conditioned signal at 1-18 is supplied via the OR gate 19, and is incremented every time the delay signal SD from the delay circuit 17 is supplied to the clock terminal.

The control circuit 16 is composed of, for example, a control ROM, in which the setting value of the pattern size setting register 14 is stored in the upper address, and the count value of the counter 15 is stored in the lower address, and based on these stored values, the address control unit @ S
AX, SAY and control signal SC are output. The control content in this case is, for example, the pattern size setting register 14.
When the set value of is rlJ and the count value of the counter 15 is "0", that is, when no expansion is performed, an address control signal SAX that increments the X address register 12 is output, and the counter 15 is cleared. Outputs signal SC. Further, when the set value of the pattern size setting register 14 is "2", that is, when performing double enlargement, the counter I value of the counter 15 changes from "0" to "3".
”.

When the count value is "0", the X address register 1
Address control information SAY that increments the number by 3 is output, and when the count value is "1", address control information SAY that increments the X address register 12 is output.
is output, and when the count value is "2", the address control information S that decrements the X address register 13 is output.
When AY is output and the count value is "3", a control signal SC for clearing the counter 15 is output. Furthermore, when the set value of the pattern size setting register 14 is "3" and the enlargement is performed three times, the count value of the counter 15 changes from "0" to "8". The count value is r
ob, rlJ, the X address register 13
When the count value is [2J, r3J, r7J, the address control signal SAX that increments the X address register 12 is sent, and when the count value is I'4j, r6J, the When the count value is "5", the address control signal SAY that decrements the X address register 12 is output, and when the count value is "8", the address control signal SAY that decrements the X address register 12 is output. It outputs an address control signal SAX that increments the counter 15 by 12, and also outputs a control signal SC that clears the counter 15.

When the display control unit 2 receives display information from an external processing device, it stores this display information, first accesses the X address register 12 and the X address register 13, and writes predetermined address data therein. , - Outputs the write control signal SR to refresh the memory 5
Write and store the first character pattern code.

Next, a write control signal SW of the pattern size setting register 15 is outputted to store the pattern size data in this register 15, and then a predetermined character pattern code is sent out and a write control signal SR is outputted.

Note that the display information sent from the external processing device includes at least a character pattern code, its address data, an identification code for whether it is a basic pattern or an enlarged pattern, etc., and the display control unit 2 executes predetermined control.

Next, the effect will be explained. First, when display information is sent to the display control unit 2 from an external processing device, the display control unit 2 transmits the address information included in the display information when the identification code included in the display information represents a basic pattern. After analysis, address data is first set in the X address register 12 and the X address register 13, and then the write control signal SW is output to write the pattern size data into the pattern size setting register 14. At this time, the counter 1 is set by the write control signal SW.
5 is cleared and the count value becomes "0". Therefore, in the control circuit 16, "1" is written to its upper address and "0" is written to its lower address, so that a control signal SC for clearing the counter 15 is output. but,
At this time, since the delay signal SD is not output from the delay circuit 17, the counter 15 is never cleared.

Next, when a character pattern code is sent from the display control section 2, it is supplied to the refresh memory 5 via the common bus 4, and at the same time, a write control signal SR is output from the display control section 2, and the character pattern code is outputted from the display control section 2. The pattern code is stored in the address position specified by the X address register 12 and the X address register 13 of the refresh memory 5. Then, since the delayed signal SD is outputted from the delay circuit 17 with a slight delay from this point, the counter 15 is incremented, but at the same time, the AND gate 1 is sent to its clear terminal.
Since the output of 8 is supplied via the OR gate 19, the counter 15 maintains a clear state.

Further, when the display information from the external processing device 3 includes an identification code representing a double enlarged pattern, the display control unit 2 first sends the address information of the first character pattern code to the X address register 12 and Write the data to the X address register 13, for example, to the upper left basic pattern of the enlarged character rAJ! (0,0
).

Next, the display control section 2 outputs a write control signal SW to set the pattern size data included in the display information of the processing device 4 as "2" in the pattern size setting register 14. At this time, the write signal SW is
Since the signal is also supplied to the clear terminal of the counter 15, the counter 15 is cleared and its count value becomes "0".

Therefore, 1. The control circuit 16 increments the X address register 13 because the setting value "2" of the pattern size setting register 14 is stored in the upper address and the count value "0" of the counter 15 is stored in the lower address. The address control signal SAY is output.

However, at this point, since the write control signal SR for the refresh memory 5 is not output from the display control section 2, the contents of the X address register 13 are not changed and remain at "0".

Next, the display control unit 2 sends the first character pattern code to the refresh memory 5 via the common bus 4.
At the same time, the write control signal SR is output to write the first character pattern code to the address position (0, 0) specified by the X address register 12 and the X address register 13 of the refresh memory 5.

Then, when the write control signal SR is output, the delay signal SD is output from the delay circuit 17 at a slightly delayed time from this point. Therefore, the contents of the X address register 13 are incremented to "1" by the address control signal SAY from the control circuit 16, and the contents of the counter 1
5 is incremented and the count value becomes "1". Therefore, when the count value of the counter 15 becomes "1", the control circuit 16 sends an address control signal SAX that increments the X address register 12.
Output.

Next, the display control unit 2 sends the next character pattern code to the refresh memory 5 via the common bus 4, and also outputs a write control signal SR to transfer the character pattern code to the refresh memory 5. Write to address location (0, 1) specified by address register 12 and Y address register 13.

Then, at a slightly delayed point from this point, the delay circuit 17
Since the delayed signal SD is output from the X address register 12, the contents of the
It is incremented by AX and becomes "1", and at the same time, the counter 15 is incremented and its count value becomes "2". Therefore, when the count value of the counter 15 becomes 12'', the control circuit 16 outputs an address control signal SAY that decrements the Y address register 13.

Next, the display control unit 2 sends the next character pattern code to the X address register 12 and the Y address L register 13 of the refresh memory 5 via the common bus 4.
Write to the address location (1, 1) specified by .

Then, when the delay signal SD is output from the delay circuit 17, the contents of the Y° address register 13 are decremented to "0" by the address control signal SAY from the control circuit 16, and the counter 15 is incremented to "0". The count value becomes "3". Therefore, when the count value of the counter 14 becomes "3", the control circuit 16 sends a control signal SC to clear the counter 15.
is output. At this time, since the delay signal SD of the delay circuit 17 is not supplied to the AND gate 18, its output is a logical value "0", and the counter 15 is not cleared.

In this state, the display control unit 2 writes the next character pattern code via the common bus 4 to the address position C1,0 specified by the X address register 12 and Y address register 13 of the refresh memory 5.

Then, when the delay signal SD is output from the delay circuit 17, the output of the AND gate 18 becomes a logical value "1", so that
The counter 15 is cleared and its count value becomes "0".

As a result of the above operations, as shown in FIG. 3(a), the address of the refresh memory 5! (0,0).

Each character pattern code r101 that constitutes the enlarged character rAJ at (0,1), (1,1), and (1,0), respectively
J, r102J, r103J and "104" will be stored. As a result, on the CRT display 9,
The enlarged characters rAJ shown in FIG. 3(b) can be displayed.

In the same way, the pattern size data represented by the basic;
By sending "3" to the pattern size setting register 14, the address positions of the refresh memory 5 are sequentially moved as shown in FIG. is stored, and characters enlarged three times as much as the basic pattern can be displayed.

In the above embodiment, a case has been described in which a pattern enlarged twice or three times as large as the basic pattern is displayed, but by changing the control contents of the control circuit 16, a pattern enlarged four times or more can be displayed. Of course, it is also possible to display only the width or height of the basic pattern by multiplying it by an integer.

Further, in the above embodiment, the control circuit 16 outputs the lightning control signals SAX, SAY, and SC, and these signals are transmitted to the X address register 12.0 by the delay signal SD. Although the case where the Y address register 13 and the counter 15 are controlled has been described, each control signal is output every time the delay signal SD is output from the control circuit 16, and the address register 12, 13 and the counter 15 are controlled based on these. You can do it like this.

Further, in the above embodiment, the case where horizontal writing is displayed has been described, but the present invention can also be applied to the case where vertical writing is displayed.

〔Effect of the invention〕

As explained above, according to the present invention, the write address of the refresh memory is controlled to be automatically moved in a predetermined order every time a character pattern code is written in accordance with the character pattern size and data. When displaying a character pattern that is a combination of multiple basic patterns such as enlarged characters, it is possible to omit processing such as address calculation and At1/pointer settings on the arithmetic processing unit that constitutes the display control unit. Therefore, the burden on the display control section can be reduced, and the processing of the arithmetic processing unit constituting the display control section can be simplified, so that effects such as improved display speed can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, FIG. 2 is a diagram showing the relationship between character pattern codes and character patterns for displaying enlarged characters, and FIG. 3 is a diagram showing the relationship between character pattern codes and character patterns for displaying enlarged characters.
l is a diagram showing the memory contents of the refresh memory and the character pattern displayed on the CRT display, respectively;
FIG. 4 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a diagram showing the storage order in which character pattern codes are stored in the refresh memory. ■...Display device, 2...Display control unit, 3...Display display unit,
4... Common bus, 5... Refresh memory, 7... Character generator, 8...
...Video control unit, 9...CRT display, 10...Refresh memory writing control device, 12...X address register, 13...
... Y address register, 14 ... Pattern setting register, 15 ... Counter, 16 ...
...control circuit. Patent applicant Fuji Electric Manufacturing Co., Ltd. Fuji Facom Control Co., Ltd. Agent Patent attorney Tetsuya Mori Agent Patent attorney Yoshiaki Naito Agent Patent attorney Shimizu Authorized agent Patent attorney Kajiyama Banaga Figure 1 ■ Figure 2

Claims (1)

[Scope of Claims] (Refresh memory for writing a character pattern code, an address register for selecting a write address of the refresh memory, and a write address of the address register, each time a character pattern code is written to the refresh memory. A fresh memory write control method, comprising: a control device for updating a character pattern in a predetermined order according to a pattern size. (2) The control device includes a pattern size setting register for setting a character pattern size; A counter that is cleared when writing is performed to the pattern size setting register and incremented each time writing is performed to the refresh memory, and a write address of the address register based on the contents of the pattern size setting register and the counter. 12. The refresh memory write control system according to claim 11, comprising a control circuit for controlling the refresh memory write control system.