JPS60111123U - differential comparator - Google Patents
differential comparatorInfo
- Publication number
- JPS60111123U JPS60111123U JP20178983U JP20178983U JPS60111123U JP S60111123 U JPS60111123 U JP S60111123U JP 20178983 U JP20178983 U JP 20178983U JP 20178983 U JP20178983 U JP 20178983U JP S60111123 U JPS60111123 U JP S60111123U
- Authority
- JP
- Japan
- Prior art keywords
- calibration
- generator
- data
- input
- data generator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 1
Landscapes
- Measurement Of Current Or Voltage (AREA)
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の差動コンパレーターの構成図、第２図は
第１図におけるタイミングチャート図、第３図は、この
考案による、差動コンパレーターの構成図、第４図は、
第３図の考案によるタイミングチャート図である。
図中、Ｑｌ、Ｑ２はソースホロワのＦＥＴＸ５は入力信
号切換スイッチ、６はデータジ−エネレータ、７はＲＡ
Ｍ、 ８は校正コマンド発生器、９はＤ／Ａコンバータ
、１０は利得−１のアンプ、Ａは被測定信号、Ｅは校正
開始コマンド、Ｆは入力信号切換えスイッチＳの開閉タ
イミング、ＧはＤ／Ａコンバータ７の出力信号、Ｈは差
動アンプＵ１の出力信号、■はＲＡＭ７の出力信号、Ｊ
は校企終了コマンドである。なお、図中、同一あるいは
相当部分には同一符号を付して示しである。Fig. 1 is a block diagram of a conventional differential comparator, Fig. 2 is a timing chart diagram of Fig. 1, Fig. 3 is a block diagram of a differential comparator according to this invention, and Fig. 4 is:
FIG. 4 is a timing chart diagram based on the invention of FIG. 3; In the figure, Ql and Q2 are source followers, FETX5 is an input signal changeover switch, 6 is a data generator, and 7 is an RA
M, 8 is a calibration command generator, 9 is a D/A converter, 10 is an amplifier with a gain of -1, A is the signal under measurement, E is a calibration start command, F is the opening/closing timing of the input signal changeover switch S, G is D /A converter 7 output signal, H is the output signal of the differential amplifier U1, ■ is the output signal of the RAM 7, J
is the school plan termination command. In the drawings, the same or corresponding parts are designated by the same reference numerals.
Claims (1)
その２個のＦＥＴの一方の入力ゲートを接地し、かつも
う一方のＦＥＴの入力ゲート端子に被測定信号と基準電
圧を重畳する差動コンパレーターにおいて、上記、基準
電圧を反転増幅するアンプと、差動コンパレーターの入
力端に、上記、アンプの出力信号と、被測定信号のどち
らか一方を選択し、印加する入力信号切換えスイッチと
前記ＦＥＴの一方のソースに補止電圧を加えるＤ／Ａコ
ンバータと、前記、補正電圧が、１分解能ステップごと
に大きくなる様なデータを発生するデータジェネレータ
と、前記データを校正期間は、前記データジェネレータ
から、前記Ｄ／Ａコ−ンバータに通過させ、又、校正期
間が終了した時の値を記憶するＲＡＭと、前記、入力信
号切換えスイッチ及び、前記データジェネレータに、校
正開始コマンド及び校正終了コマンドとを送る、校正コ
マンド発生器とを有する事を特徴とする差動コンツマレ
ータ−While connecting two gate type FETs to the input circuit,
In a differential comparator that has one input gate of the two FETs grounded and superimposes the signal under test and a reference voltage on the input gate terminal of the other FET, the amplifier that inverts and amplifies the reference voltage; A D/A that selects either the output signal of the amplifier or the signal to be measured and applies a supplementary voltage to the input terminal of the differential comparator and the source of one of the FETs. a converter; a data generator that generates data such that the correction voltage increases for each resolution step; and a data generator that passes the data from the data generator to the D/A converter during a calibration period; , comprising a RAM that stores a value at the end of a calibration period, and a calibration command generator that sends a calibration start command and a calibration end command to the input signal changeover switch and the data generator. Differential contour generator
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20178983U JPS60111123U (en) | 1983-12-27 | 1983-12-27 | differential comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20178983U JPS60111123U (en) | 1983-12-27 | 1983-12-27 | differential comparator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60111123U true JPS60111123U (en) | 1985-07-27 |
Family
ID=30763904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20178983U Pending JPS60111123U (en) | 1983-12-27 | 1983-12-27 | differential comparator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60111123U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5633768U (en) * | 1979-08-24 | 1981-04-02 |
-
1983
- 1983-12-27 JP JP20178983U patent/JPS60111123U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5633768U (en) * | 1979-08-24 | 1981-04-02 |
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