JPS60110173A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60110173A JPS60110173A JP58218926A JP21892683A JPS60110173A JP S60110173 A JPS60110173 A JP S60110173A JP 58218926 A JP58218926 A JP 58218926A JP 21892683 A JP21892683 A JP 21892683A JP S60110173 A JPS60110173 A JP S60110173A
- Authority
- JP
- Japan
- Prior art keywords
- region
- source
- gate
- electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 230000000694 effects Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 108091006146 Channels Proteins 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/80—FETs having rectifying junction gate electrodes
Landscapes
- Led Devices (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置、特には電界効果型トランジスタに
関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor devices, and in particular to field effect transistors.
従来例の構成とその問題点
電界効果型トランジスタ（以下ＦＥＴと略す）の高速・
高周波化のためには相互コンダクタンスｇｍの増大が必
要である。従来がらＦＥＴの高ｇｍ化のためにはゲート
長の微細化などが行われており、１だ一方ではソース抵
抗Ｒ８の低減化が行われている。Ｒ８の低減化は通常の
ホトリソ技術に頼っていては大きな効果が期待できない
ので、アンダーエツチング技術とセルファライン技術と
によりソース・ゲート間を微細化してＲ９ｆｆ：減少す
る技術の開発が進められ−〔いる。Conventional configuration and its problems High-speed and
In order to increase the frequency, it is necessary to increase the mutual conductance gm. Conventionally, in order to increase the gm of FETs, the gate length has been made smaller, and on the other hand, the source resistance R8 has been reduced. Relying on ordinary photolithography technology cannot be expected to have a great effect on reducing R8, so the development of technology to reduce R9ff by miniaturizing the source-gate gap using under-etching technology and self-line technology is progressing. There is.
しかしながらアンダーエツチング技術はアンダーエツチ
ング量の制御性、再現性、基板面内での均一性が悪＜−
ｘｃ 、ＬＳＩの製造には適さないと思われる。また基
板面内での不均一性に伴い。However, under-etching technology has poor controllability, reproducibility, and uniformity of the under-etching amount within the substrate surface.
xc, it seems not suitable for LSI manufacturing. Also, due to non-uniformity within the substrate surface.
ゲートパターンを任意の方向・場所に形成するパターン
自由度も小さいという欠点もある。Another drawback is that the degree of freedom in patterning the gate pattern in any direction and location is small.
発明の目的 本発明に上記欠点に鑑みてなされたものであり。purpose of invention The present invention has been made in view of the above drawbacks.
通常のホトリソ技術によｐ ｌ（Ｓを著しく低減した高
ｇｍを有する半導体装置を提供するものである。The present invention provides a semiconductor device having a high gm with significantly reduced pl(S) using ordinary photolithography technology.
発明の構成
本発明の半導体装置にソース領域、ゲート領域およびド
レイン領域を有する半導体装置において少なくとも前記
ソース領域と前記ゲート領域間にソース抵抗を減少させ
るべく発光手段を・有することによ多構成される。Structure of the Invention The semiconductor device of the present invention has a source region, a gate region, and a drain region, and the semiconductor device has a light emitting means between at least the source region and the gate region to reduce source resistance. .
実施例の説明
一般に化合物半導体に光に対して非常に敏感であり一化
合物半導体の表面に光を照射すると光導電効果により前
記半導体の抵抗に通常２桁程度減少することが知られて
いる。本発明は上述の光導電効果に基づいてなさｆｌた
ものであり−ＮＥＴの少なくともソース領域とゲート領
域間に発光手段を有し、前記発光手段によシソース領域
とゲート領域間に光導電効果を生ぜしめ、ソース抵抗を
減少しｇｍヲ増大させるものである。以下本発明を実施
例を用いて詳細に説明する０
第１図ａ本発明の半導体装置の第１の実施例を示す断面
図である。１１は半絶縁性Ｇ２ＬＡ５基板。DESCRIPTION OF THE EMBODIMENTS Compound semiconductors are generally very sensitive to light, and it is known that when the surface of a single compound semiconductor is irradiated with light, the resistance of the semiconductor usually decreases by about two orders of magnitude due to the photoconductive effect. The present invention is based on the photoconductive effect described above, and includes a light emitting means between at least the source region and the gate region of the NET, and the light emitting means produces a photoconductive effect between the source region and the gate region. This reduces source resistance and increases gm. The present invention will be described in detail below using examples. FIG. 1a is a sectional view showing a first example of a semiconductor device of the present invention. 11 is a semi-insulating G2LA5 board.
１２にｎ形チャネル領域、１３けソース領域１４および
ドレイン領域１６に形成されているｎ＋形領領域１６は
ゲート領域、１７ｒよソース電極、１８ａドレイン電極
、１９にゲート電極、２０はソース領域１４とゲート領
域１６間のソース・ゲート間領域２１に形成された制御
電極であシ、制御電Ｔｈ２０とチャネル領域１２．ｎ＋
形領領域１３よびソース電極１７とにより発光手段２２
を形成している。ソース電極１７お・よびドレイン電極
１８は人ｕ−（：、ｅ ／ Ｎｉにより、ゲート電極１
９お・よび市１ｊ御電極２０はＰｔにより形成した。ゲ
ート長は１μｍ−ゲート幅Ｖ：Ｌ２０μｍ、ソース・ゲ
ート間領域２１の長さに２μｍである。12 is an n-type channel region, 13 is a source region 14 and a drain region 16, and the n+-type region 16 is a gate region, 17r is a source electrode, 18a is a drain electrode, 19 is a gate electrode, and 20 is a source region 14. The control electrode formed in the source-gate region 21 between the gate region 16, the control electrode Th20 and the channel region 12. n+
The light emitting means 22 is formed by the shaped region 13 and the source electrode 17.
is formed. The source electrode 17 and the drain electrode 18 are made of a metal u-(:, e/Ni), and the gate electrode 1
The control electrodes 9 and 1j were made of Pt. The gate length is 1 μm−gate width V:L20 μm, and the length of the source-gate region 21 is 2 μm.
第１図に示すＥ型（エンノ・ンスメント型） ＦｇＴに
おいて、電極２ｏに電圧を印加しな力）つた場合のソー
ス抵抗１（！にＪ１００Ω、その時のｇｍ Ｒ２、ｓｍ
ｓ であった。−力制御電極２０とソース電＠１７間に
制御電極２０が負の電位となるように制御電圧を印加し
たところ、ソース抵抗Ｒ８に１０Ωと著しく減少し、ｇ
ｍ は４．０１１１３と向上した。これは電極２０から
ソース電極１７に１ｉｌｉ］力為って電子を注入したこ
とに工り赤外光力玉発生し、それによりソース・ゲート
間領域２１のチャネル領域１２内に光導電効果が生じ、
したカニッてソース抵抗Ｒｓが１００Ωから１０Ωへと
減少したものと思われる。In the E-type (enhancement type) FgT shown in Figure 1, when a voltage is not applied to the electrode 2o, the source resistance 1 (!) is J100Ω, then gm R2, sm
It was s. - When a control voltage was applied between the force control electrode 20 and the source voltage @17 so that the control electrode 20 had a negative potential, the source resistance R8 significantly decreased to 10Ω, and g
m improved to 4.01113. This is due to the injection of electrons from the electrode 20 to the source electrode 17, which generates an infrared light beam, which causes a photoconductive effect in the channel region 12 of the source-gate region 21. ,
It is thought that this caused the source resistance Rs to decrease from 100Ω to 10Ω.
一方ソース・ゲート間領域の長さが１μｍで。On the other hand, the length of the region between the source and gate is 1 μm.
ソース・ゲート間領域に制御電極２０を有しない通常の
構造のＥ型ＦＩＴにおいては、ソース抵抗Ｒ５は６０Ω
−ｇｍはａ、ｏｍｓであり一通當の構造（ソース・ゲー
ト間領域２１に制御電極２０を有さず−したがってソー
ス・ゲート間領域２１の長さが１μｍ ）のＥ型ＦＥＴ
と比較してもＲｓが６０Ωから１０Ωへと、またｇｍも
ｓ、ｏ ｍｓ から４ 、Ｏｍｓ へと向上しているこ
とがわかる。In an E-type FIT with a normal structure that does not have a control electrode 20 in the region between the source and gate, the source resistance R5 is 60Ω.
- gm is a, oms, and it is an E-type FET with a one-piece structure (no control electrode 20 in the source-gate region 21 - therefore, the length of the source-gate region 21 is 1 μm)
It can be seen that Rs has improved from 60Ω to 10Ω, and gm has also improved from s, oms to 4, oms.
第２図は本発明の第２の実施例を示す断面図であシ、第
１図と同一個所に同一番号で示している。FIG. 2 is a sectional view showing a second embodiment of the present invention, and the same parts and numbers as in FIG. 1 are indicated by the same numbers.
第２の実施例では前述した通常の構造のＥ型ＦｊＣＴに
おいて、ソース・ゲート間領域２１０表面に絶嶽膜を介
して蒸着法で製造した発光手段を形成した。３２は前１
己発光手段を示しており、ソース・ゲート間領域２１に
プラズマＣｖＤ法によって形成された窒化シリコン膜か
らなる絶縁膜３１を介して形成されている。３３１１透
明電極、３４はｐ形ＺｎＳ、３５はｎ形ＺｎＳ−３６ｉ
’ｊ表面電極である。In the second example, in the above-mentioned E-type FjCT with the normal structure, a light emitting means manufactured by vapor deposition was formed on the surface of the source-gate region 210 via an insulating film. 32 is front 1
A self-luminous means is shown, which is formed in the source-gate region 21 via an insulating film 31 made of a silicon nitride film formed by plasma CVD method. 3311 transparent electrode, 34 is p-type ZnS, 35 is n-type ZnS-36i
'j is a surface electrode.
発光手段３２に電圧を印加しない場合の第２図（７）Ｋ
型ＮＥＴの７−、Ｘ抵抗Ｒ５Ｉｒ１ｅｏΩ−ｇｎａｔｓ
、ｏｍｓであった。一方前記発光手段３２に、透明電極
３３側が正となるように電圧を印加した場合、ソース抵
抗Ｒ５１７Ωヘ−ｇｍ Ｈ４，５ｍＳ ヘと向上した。FIG. 2 (7) K when no voltage is applied to the light emitting means 32
7-, X resistance R5Ir1eoΩ-gnats of type NET
, oms. On the other hand, when a voltage was applied to the light emitting means 32 so that the side of the transparent electrode 33 was positive, the source resistance was improved to R517Ω - gm H4,5mS.
以上の本発明の第１および第２の実施例に示した発光手
段はこれらに限定されるものではなく、注入型あるいに
電界型、誘導放出型発光手段など種々の発光手段を用い
ることができ、材料もＳｉなどの■族半導体、［−■族
あるいはｌＩ −’Ｖｌ族化合物半導体およびそれらの
混晶半導体など種々の材料とすることができ、それらの
製造方法も蒸着法に限定されるものではない。捷たＦＥ
Ｔを製造する半導体基板もＧａＡＳ基板に限られるもの
ではな（−５ｉなとの■族半導体、ｌ−Ｖ族あるいはＵ
−ＶＩ族化合物半導体およびそれらの混晶半導体など種
々の半導体基板を用いることができ、またＦＥＴの種類
もＭＫＳＦＥＴ 、ＭＯＳＦＥＴ 。The light emitting means shown in the first and second embodiments of the present invention are not limited to these, and various light emitting means such as injection type, electric field type, and stimulated emission type can be used. Various materials can be used, such as group II semiconductors such as Si, [-■ group or lI-'Vl group compound semiconductors, and mixed crystal semiconductors thereof, and the manufacturing method thereof is also limited to vapor deposition. It's not a thing. Discarded FE
Semiconductor substrates for manufacturing T are not limited to GaAS substrates (-5i group semiconductors, l-V group semiconductors, or U-group semiconductors).
-Various semiconductor substrates such as Group VI compound semiconductors and their mixed crystal semiconductors can be used, and types of FETs include MKSFET and MOSFET.
ＭＩＳＦＥＴあるいはＪＦ’ＥＴなど種々変更可能であ
る。さらにＦＩＴの型もＥ型に限られるものでにない。Various modifications such as MISFET or JF'ET are possible. Furthermore, the type of FIT is not limited to the E type.
発明の効果
以上の説明で明らか々ように、ソース領域とゲート領域
間に発光手段を有した本発明の半導体装置により１通常
のホトリソ技術を用いてソース抵抗Ｒｓが著しく減少し
、したがって相互フンダクタンスｇｍの増大した半導体
装置を得ることができた。本発明の半導体装置は通常の
ホトリソ技術を用いて製造可能であるため、加工の制御
性、再現性、均一性に優ｎ−歩留まシが向上する。１だ
それ故ＩＣ、ＬＳＩの製造にも適している。さらにパタ
ーンの自由度も極めて犬である。Effects of the Invention As is clear from the above explanation, the semiconductor device of the present invention having a light emitting means between the source region and the gate region can significantly reduce the source resistance Rs by using ordinary photolithography technology, and therefore reduce the mutual fundance. A semiconductor device with increased gm could be obtained. Since the semiconductor device of the present invention can be manufactured using ordinary photolithography technology, the controllability, reproducibility, and uniformity of processing are excellent, and the yield rate is improved. 1. Therefore, it is also suitable for manufacturing ICs and LSIs. Furthermore, the degree of freedom in patterns is extremely unique.
なお以上の実施例では発光手段をソース・ゲート間領域
に形成したがこの領域に限られるものではなく、ソース
・ドレイン間領域全面に形成しても良い。またソース・
ゲート間領域およりゲート・ドレイン間領域に形成して
も良い。In the above embodiments, the light emitting means is formed in the region between the source and the gate, but it is not limited to this region, and may be formed over the entire region between the source and the drain. Also sauce
It may be formed in the inter-gate region or the gate-drain region.
第１図および第２図は本発明の半導体装置の第１および
第２の実施例を示す断面図である。
１１・・・・・・ＧａＡＳ基板−１２・・・・・・ｎ形
チャネル領域、１４・・・・・・ソース領域＋１６・・
・・・−ドレイン領域。
１６・・・・・・ゲート領域、２１・・・・・・ソース
・ゲート間領域−２２，３２・・・・発光手段。1 and 2 are cross-sectional views showing first and second embodiments of the semiconductor device of the present invention. 11...GaAS substrate-12...n-type channel region, 14...source region +16...
...-Drain region. 16... Gate region, 21... Source-gate region -22, 32... Light emitting means.
Claims (1)
なくとも前記ソース領域と前記ゲート領域間に発光手段
を有し、前記うら元手段によりソース抵抗を減少させる
ことを特徴とする半導体装置。1. A semiconductor device comprising a source region, a gate region and a drain region, a light emitting means between at least the source region and the gate region, and a source resistance reduced by the ridge means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58218926A JPS60110173A (en) | 1983-11-21 | 1983-11-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58218926A JPS60110173A (en) | 1983-11-21 | 1983-11-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60110173A true JPS60110173A (en) | 1985-06-15 |
Family
ID=16727481
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58218926A Pending JPS60110173A (en) | 1983-11-21 | 1983-11-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60110173A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6355978A (en) * | 1986-08-26 | 1988-03-10 | Yokogawa Electric Corp | Semiconductor device |
| WO2014184995A1 (en) * | 2013-05-16 | 2014-11-20 | パナソニックＩｐマネジメント株式会社 | Nitride semiconductor device |
| WO2016185645A1 (en) * | 2015-05-21 | 2016-11-24 | パナソニック株式会社 | Nitride semiconductor device |
| US10946887B2 (en) | 2018-05-28 | 2021-03-16 | Mitsubishi Logisnext Co., LTD. | Steering device and cargo handling vehicle |
-
1983
- 1983-11-21 JP JP58218926A patent/JPS60110173A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6355978A (en) * | 1986-08-26 | 1988-03-10 | Yokogawa Electric Corp | Semiconductor device |
| WO2014184995A1 (en) * | 2013-05-16 | 2014-11-20 | パナソニックＩｐマネジメント株式会社 | Nitride semiconductor device |
| JPWO2014184995A1 (en) * | 2013-05-16 | 2017-02-23 | パナソニックＩｐマネジメント株式会社 | Nitride semiconductor device |
| US9680053B2 (en) | 2013-05-16 | 2017-06-13 | Panasonic Intellectual Property Management Co., Ltd. | Nitride semiconductor device |
| WO2016185645A1 (en) * | 2015-05-21 | 2016-11-24 | パナソニック株式会社 | Nitride semiconductor device |
| JPWO2016185645A1 (en) * | 2015-05-21 | 2018-03-15 | パナソニック株式会社 | Nitride semiconductor device |
| US10946887B2 (en) | 2018-05-28 | 2021-03-16 | Mitsubishi Logisnext Co., LTD. | Steering device and cargo handling vehicle |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5448096A (en) | Semiconductor device with reduced stress applied to gate electrode | |
| US3883372A (en) | Method of making a planar graded channel MOS transistor | |
| US4559693A (en) | Process for fabricating field effect transistors | |
| KR900000584B1 (en) | Semiconductor integrated circuit device | |
| JPS60110173A (en) | Semiconductor device | |
| JPS6437057A (en) | Thin film field effect transistor | |
| JPH0322064B2 (en) | ||
| JPH0329326A (en) | Junction field-effect transistor | |
| EP0107039B1 (en) | Resonant transmission semiconductor device and circuit including such a device | |
| JPS6123364A (en) | Field effect transistor | |
| JPS61232682A (en) | Field effect transistor | |
| JP3090451B2 (en) | Semiconductor device | |
| JPS60176277A (en) | gallium arsenide integrated circuit | |
| Decelercq et al. | A theoretical and experimental study of DMOS enhancement/depletion logic | |
| JPS6244698B2 (en) | ||
| JPH0249439A (en) | field effect transistor | |
| JPS58124276A (en) | Schottky gate field effect transistor and manufacture thereof | |
| JPS61237473A (en) | field effect transistor | |
| JPS60134479A (en) | Semiconductor device | |
| JPS62195178A (en) | Manufacture of gaas schottky gate field effect transistor | |
| JPS61202470A (en) | semiconductor equipment | |
| JPH0346369A (en) | Insulated gate type field effect transistor | |
| JPS61161771A (en) | shot key gate field effect transistor | |
| JPS61265870A (en) | Method for manufacturing field effect transistors | |
| JPS57160170A (en) | Field effect semiconductor device |