JPS60107938A - Multiplexing method of binary signal - Google Patents
Multiplexing method of binary signalInfo
- Publication number
- JPS60107938A JPS60107938A JP58214051A JP21405183A JPS60107938A JP S60107938 A JPS60107938 A JP S60107938A JP 58214051 A JP58214051 A JP 58214051A JP 21405183 A JP21405183 A JP 21405183A JP S60107938 A JPS60107938 A JP S60107938A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- binary
- gate
- binary signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 11
- 230000005540 biological transmission Effects 0.000 claims description 9
- 238000007493 shaping process Methods 0.000 abstract description 4
- 230000008054 signal transmission Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 230000004069 differentiation Effects 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L7/044—Speed or phase control by synchronisation signals using special codes as synchronising signal using a single bit, e.g. start stop bit
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
Abstract
Description
【発明の詳細な説明】
(技術分野)
本発明は、2値付号伝送路での2つの2値信号の多重化
方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for multiplexing two binary signals on a binary coded transmission path.
(背景技術)
従来の多重化方法の一例を第1図に示す。この方法によ
シ2つの2値信号A及びBを多重化する場合、2値付号
八入力端子1.2値信号B入力端子2及び同期信号発生
回路3の各々に対し、セレクタ4の切替によシ時間的な
割シ当てを行ない、割シ当てられた時間に各状態を2値
付号伝送路5を介して伝送する。そして受信側では同期
信号検出回路8に合わせてDフリアゾフロップ6.7の
論理によ#)2値信号AとBとを識別し、それぞれの信
号を出力端子9または10に実現するようになっている
。しかしながら、このような従来の多重化方法では、上
述のごとく割シ当てられた時間に各状態を伝送するので
、各々の割シ当て時間を識別する為の同期信号もあわせ
て伝送しなければならないという欠点があった。(Background Art) An example of a conventional multiplexing method is shown in FIG. When multiplexing two binary signals A and B using this method, the selector 4 is switched for each of the binary signal numbered 8 input terminal 1, the binary signal B input terminal 2, and the synchronization signal generation circuit 3. Each state is transmitted via the binary coding transmission line 5 at the assigned time. Then, on the receiving side, binary signals A and B are identified according to the logic of the D-friazo flop 6.7 according to the synchronization signal detection circuit 8, and the respective signals are realized at the output terminal 9 or 10. It has become. However, in such conventional multiplexing methods, each state is transmitted at the allocated time as described above, so a synchronization signal for identifying each allocated time must also be transmitted. There was a drawback.
(発明の課題)
本発明は上述のごとき欠点を除去するためなされたもの
であって、同期信号の伝送が不要な2値付号多重化方法
を提供することを目的とするもので、以下詳細に説明す
る。(Problems to be solved by the invention) The present invention has been made to eliminate the above-mentioned drawbacks, and its purpose is to provide a binary code multiplexing method that does not require the transmission of synchronization signals. Explain.
(発明の構成及び作用)
第2図は本発明の方法を適用した一実施例のブ゛ロック
図であシ、第3図(、)〜(f)はそのタイムチャート
である。(Structure and operation of the invention) FIG. 2 is a block diagram of an embodiment to which the method of the invention is applied, and FIGS. 3(,) to (f) are time charts thereof.
第2図において、21は2値化号八入力端子、22は2
値化号B入力端子、23はイクスクルーシゾOR(排他
的論理和)ゲート、24笈び31はANDダート、25
はパルス発振器、26は2値化号伝送路、27はロー・
ぐスフィルタ、28は波形整形回路、29は微分回路、
30及び32は単安定マルチバイブレータ、33は2値
化号人出力端子、34は2値化号B出力端子である。2
値化号B入力端子22とiRパルス振器25はANDゲ
ート24に接続され、ANDゲート24の出力はイクス
クルーシブORゲート23の1つの入力に接続されてい
る。一方、2値化号A入力端子22はイクスクルーシブ
ORゲート23の他方の入力に接続されている。イクス
クルーシブORゲート23の出力は2値化号伝送路26
を介して受信側と連結される。受信側において伝送路2
6はローパスフィルタ27及び微分回路29に接続され
、ローパスフィルタ27の出力は波形整形回路28を介
して2値化号A出力端子33に接続される。一方、微分
回路29の出力は単安定マルチバイブレータ30と接続
されると共にに0ゲート31の1つの入力に接続されて
いる。にΦゲート31のもう1つの入力は単安定マルチ
バイブレータ30の出力と接続されている。そしてAN
Dグー)31の出力は単安定tZイブレータ32を介し
て2値化号B出力端子34と接続される。In FIG. 2, 21 is a binary input terminal, and 22 is a 2
Value code B input terminal, 23 is exclusive OR (exclusive OR) gate, 24 and 31 are AND dart, 25
is a pulse oscillator, 26 is a binary signal transmission line, and 27 is a low signal transmission line.
28 is a waveform shaping circuit, 29 is a differentiation circuit,
30 and 32 are monostable multivibrators, 33 is a binary signal output terminal, and 34 is a binary signal B output terminal. 2
The value signal B input terminal 22 and the iR pulse generator 25 are connected to an AND gate 24, and the output of the AND gate 24 is connected to one input of the exclusive OR gate 23. On the other hand, the binary signal A input terminal 22 is connected to the other input of the exclusive OR gate 23. The output of the exclusive OR gate 23 is the binary signal transmission line 26
is connected to the receiving side via. Transmission line 2 on the receiving side
6 is connected to a low-pass filter 27 and a differentiation circuit 29, and the output of the low-pass filter 27 is connected to a binarization signal A output terminal 33 via a waveform shaping circuit 28. On the other hand, the output of the differentiating circuit 29 is connected to a monostable multivibrator 30 and to one input of a 0 gate 31. Another input of the Φ gate 31 is connected to the output of the monostable multivibrator 30. And AN
The output of the D.G.) 31 is connected to the binarization signal B output terminal 34 via the monostable tZ ibrator 32.
上記のごとき構成を有する本実施例の動作について説明
すると、2値化号B入力端子22の状1μ(第3図(a
))がrlJのときには、パルス発振器25からのデユ
ーティの小さい繰返し信号(第3図(C))がANDゲ
ート24の出力とな)、この出力信号と2値化号A(第
3図(a))との排他的論理和信号(第3図(d))を
2値化号伝送路26を介して送信する。一方、2値化号
B入力端子22の状態が「0」のときには、ANDゲー
ト24の出力は0とな)、2値化号Aをそのまま2値化
号伝送路26を介して送信する。To explain the operation of this embodiment having the above configuration, the shape of the binarization signal B input terminal 22 is 1μ (Fig. 3(a)
)) is rlJ, the repetitive signal with a small duty from the pulse oscillator 25 (FIG. 3(C)) is the output of the AND gate 24), and this output signal and the binary code A (FIG. 3(a) )) and an exclusive OR signal (FIG. 3(d)) is transmitted via the binary code transmission path 26. On the other hand, when the state of the binary code B input terminal 22 is "0", the output of the AND gate 24 is 0), and the binary code A is transmitted as it is via the binary code transmission line 26.
この様にして多重化され伝送路26を介して送信側に伝
送された信号は、ローパスフィルタ27によシ、ノクル
ス発保器25からの・ぐルス成分を除去した後、波形整
形回路28で波形整形され、2値化号A出力端子33に
て2値化号Aが再現される。また多重化された信号は、
微分回路にて信号変化分が取シ出され、この信号で単安
定マルチバイブレータ30をトリガする。ここで単安定
マルチバイブレータ30及び32の出力時間幅はパルス
発振器25の繰シ返し周期の1.5倍に設定しておくも
のとする。従って、微分回路29の出力がこの時間以内
に続いてあったときのみ単安定マルチバイブレータ32
がトリがされ、その場合、2値化号B出力端子34にて
2値化号Bが再現される。The signal multiplexed in this manner and transmitted to the transmitting side via the transmission path 26 is passed through a low-pass filter 27 to remove the . The waveform is shaped, and the binary signal A is reproduced at the binary signal A output terminal 33. Also, the multiplexed signal is
A signal change is extracted by a differentiating circuit, and the monostable multivibrator 30 is triggered by this signal. Here, it is assumed that the output time width of the monostable multivibrators 30 and 32 is set to 1.5 times the repetition period of the pulse oscillator 25. Therefore, only when the output of the differentiating circuit 29 continues within this time, the monostable multivibrator 32
In this case, the binarized signal B is reproduced at the binarized signal B output terminal 34.
以上説明したように、本実施例では、ローパスフィルタ
やパルスの連続性を検出すること等により2つの信号を
再現するので、同期信号の伝送が不要となシ、従って同
期確立までの時間や同期はずれがない利点がある。As explained above, in this embodiment, the two signals are reproduced by using a low-pass filter or by detecting the continuity of pulses, so there is no need to transmit a synchronization signal. It has the advantage of not being out of place.
(発明の効果)
本発明によれば、同期信号の伝送が不要となシ、同期確
立までの時間や同期はずれがない利点があシ、光ファイ
バを使用した2値伝送路の多重化等に利用することがで
きる。(Effects of the Invention) According to the present invention, there is an advantage that there is no need to transmit a synchronization signal, there is no time required to establish synchronization, there is no loss of synchronization, and it is suitable for multiplexing binary transmission lines using optical fibers. can be used.
第1図は従来の多重化方法を示す図、第2図は本発明多
重化方法を適用して一実施例を示す図、第3図(、)〜
(f)は上記実施例のタイムチャートである。
1.21・・・2値化号A入力端子、2,22・・・2
値化号B入力端子、3・・・同期信号発生回路、4・・
・セレクタ、5,26・・・2値化号伝送路、6,7・
・・Dタイプフリッゾフロッゾ、8・・・同期信号検出
回路、9,33・・・2値化号A出力端子、IQ、34
・・・2値化号B出力端子、23・・・イクスクルーン
ブORダート、24.31・・・ANDゲーゲー、25
・・・ノぞルス発振器、27・・・ローパスフィルタ、
28・・・波形整形回路、29・・・微分回路、30.
32・・・単安定マルチバイブレータ。Fig. 1 is a diagram showing a conventional multiplexing method, Fig. 2 is a diagram showing an embodiment of the multiplexing method of the present invention, and Figs.
(f) is a time chart of the above embodiment. 1.21...Binarization signal A input terminal, 2,22...2
Value code B input terminal, 3...Synchronization signal generation circuit, 4...
・Selector, 5, 26...Binarization signal transmission line, 6, 7・
...D type Frizzo Frozzo, 8...Synchronization signal detection circuit, 9, 33...Binarization signal A output terminal, IQ, 34
...Binarization signal B output terminal, 23...Exclude OR dirt, 24.31...AND game, 25
...Nozzles oscillator, 27...Low pass filter,
28... Waveform shaping circuit, 29... Differential circuit, 30.
32... Monostable multivibrator.
Claims (1)
多重化方法において、前記第1及び第2の2値信号よシ
周期が短かくかつデユーティの小さい・ぐルス信号と前
記第2の2値信号との論理積をとシ、前記論理積によシ
得られる信号と前記第1の2値信号との排他的論理和信
号を伝送することを特徴とする2値付号多重化方法。In a method for multiplexing a first binary signal and a second binary signal on a binary coded transmission path, the first and second binary signals have a short period and a small duty. A logical product of the signal and the second binary signal is performed, and an exclusive OR signal of the signal obtained by the logical product and the first binary signal is transmitted. Valued sign multiplexing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58214051A JPS60107938A (en) | 1983-11-16 | 1983-11-16 | Multiplexing method of binary signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58214051A JPS60107938A (en) | 1983-11-16 | 1983-11-16 | Multiplexing method of binary signal |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60107938A true JPS60107938A (en) | 1985-06-13 |
Family
ID=16649447
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58214051A Pending JPS60107938A (en) | 1983-11-16 | 1983-11-16 | Multiplexing method of binary signal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60107938A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005091544A1 (en) * | 2004-03-16 | 2005-09-29 | Boomer James B | Bit clock with embedded word clock boundary |
US7064690B2 (en) | 2004-04-15 | 2006-06-20 | Fairchild Semiconductor Corporation | Sending and/or receiving serial data with bit timing and parallel data conversion |
US7248122B2 (en) | 2005-09-14 | 2007-07-24 | Fairchild Semiconductor Corporation | Method and apparatus for generating a serial clock without a PLL |
-
1983
- 1983-11-16 JP JP58214051A patent/JPS60107938A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005091544A1 (en) * | 2004-03-16 | 2005-09-29 | Boomer James B | Bit clock with embedded word clock boundary |
US7064690B2 (en) | 2004-04-15 | 2006-06-20 | Fairchild Semiconductor Corporation | Sending and/or receiving serial data with bit timing and parallel data conversion |
US7248122B2 (en) | 2005-09-14 | 2007-07-24 | Fairchild Semiconductor Corporation | Method and apparatus for generating a serial clock without a PLL |
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