JPS60107922A - Code error detection circuit - Google Patents

Abstract

PURPOSE:To allow the use of a code error detecting circuit even when the bit rate of a transmit signal is 100Mb/sec by providing a means which outputs a limit signal when the counted value of an up/down counter exceeds a specific range. CONSTITUTION:When an optical transmission system perform nBmB conversion so that a running digital sum (RDS) is within the specific range, the running digital sum is calculated, and a decision circuit decides that a code error occurs when the sum exceeds the specific range. This circuit consists of the U/D counter 6 which follows up the bit rate of the transmit signal even above 100Mb/sec a selector 7, an FF8, NOR circuits 9 and 10, and OR circuits 11 and 12, so this circuit is usable as the code error detecting circuit even when the bit rate of input data attains to 100Mb/sec.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical field of the invention The present invention provides an optical transmission system that converts the RDS to within a predetermined range when nBmB conversion is performed so that the running digital sum (hereinafter referred to as RDS) falls within a predetermined range. Regarding the code error detection circuit that determines that code error 9 has occurred when the value exceeds the predetermined range, the pit rate of transmission number 48 is 100 Mb/s.
0(b) related to a code error detection circuit that can be realized even in a case as early as ee.Technical background What is RDS?
This is the cumulative value when counted as −1°+1.

(e) Prior Art and Problems FIG. 1 is a block diagram of a conventional code error detection circuit.

In the figure, 1 is an accumulative adder, and 2 is a flip-flop (hereinafter referred to as FF).
), 3.4 is a comparator, and 5 is an OR circuit.

To explain one operation, when data of °゛1°゛ or °゛0°'' is input to accumulative adder 1, accumulative adder 1 emits a noculus, FF2 is set by this pulse, and outputs a signal of sylvel. , are packed in the cumulative adder 1.The cumulative adder 1 performs cumulative addition by adding 1 if the data is 1 and subtracting 1 if the data is O every time a pulse from FF2 arrives. The cumulative addition value is input to a comparator 3.4.The comparator 3.4 receives a comparison value of -N which is a predetermined range of RDS.

10N is used as a cent, and the cumulative addition value to be input is less than -N. +N, l:,! 17, the comparator 3 or 4 emits a pulse as a detection signal. In this way, code errors are detected by calculating the cumulative addition value.

However, the bit rate of transmission (i) is 100Mb/see
When K, the cumulative adder 1 and the comparators 3 and 4 cannot follow this and cannot be used in such a case; (d) Purpose of the Invention The purpose of the present invention is to improve the transmission An object of the present invention is to provide a code error detection circuit that can be used even when the signal bit rate is 100 Mb/5ecK7.

(e) Structure of the Invention In order to achieve the above object, the present invention provides an up/down counter and a selector in which the pit rate of the transmission signal is 100M.
Focusing on the fact that there are things that can be tracked even with b/gee, set a predetermined range for the up/down counter and RDS that count down and count up when the data l OII T″1′° is input and input the count value to the selector. If the selector outputs a limit signal when the input count value exceeds the predetermined range, and the limit signal inputs data that causes the count value of the up/down counter to fall within the predetermined range, an error occurs. The up/down counter is configured by means for outputting a detection signal and holding the up/down counter until data that brings the count value within the predetermined range is input.

(f) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of a code error detection circuit according to an embodiment of the present invention.

In the figure, 6 is an up/down counter (hereinafter referred to as a U-D counter), 7 is a selector, 8 is an FF, 9.10 is a NOR circuit, and 11.12 is an OR circuit.The U-D counter 6 is an input terminal S. . It is controlled as shown in the table below by the 1 and 0 levels input to Sl.

Furthermore, signals corresponding to 1 and 2.4 t1 are outputted from the outputs Qo, Q+, and Qt, respectively.

Input terminal S of selector 7. When a signal is input to 181 + Sg, 7i1, 2 . , it is recognized that the value of i has been input. Also, Mizuko A0~AT and B0~B are respectively ILO~
Corresponds to the value of 7, and in Fig. 2, A0 to A, and B, to B6
H level AIIIA? and B,,B.

When the value input to the input terminals 80 to s8 becomes 6 or more, the output terminal ZA emits a pulse of L level, and when the input value becomes 1 or less, the output terminal Z
From B 1. Emit a level pulse. Therefore, if the input value is in the range of 2 to 5, no pulse will be emitted from the output terminal ZAZB. In the case of FIG. 2, the predetermined range of RDS is ±2, and this range of 2 to 5 corresponds to this range.

Figure 2 shows the code 1 when the predetermined range of RDS is ±2.
14b is an example of a detection circuit. When the data input to the FF8 is °°11', the output 1 of the FF8 becomes a level and 0 becomes a 0 level, and when the data is It OII, the output 1 of the FF8 becomes a 0 level and 0 becomes a level. Therefore, the U-D counter 6 counts up when the data is III+,
When the data is 1°OII, a countdown is performed, and the accumulated value, ie, RDS, is output from the output terminals Q0 to Q. In this case, output terminal Q. The value output from -Q is 4 when it counts down to 11, and 3 when it counts down to b.
U@D When the output of the counter 6 exceeds 6 or 1, that is, the predetermined range of RDS, the output terminal ZA or Zn of the selector 7
When a high-level pulse is output, the NOR circuit IO or 9
Enter. When the O level is output from the output terminal ZA, when a take of °I ++ is input to FF8,
The outputs of the OR circuits 11 and 12 hold the UD counter 6 and stop the counting operation. Bold continues until the data of °°0 ++ is input to FF"8.Also, when the 0 level is output from the output terminal ZB, if the data of °'0"1 is input to FF8, the OR circuit 11.12 The output of is Lebel, and U-
The D counter 6 is held and the counting operation is stopped, and an error detection signal is generated from the output of the NOR circuit 11.

This halt of the UeD counter 6 continues until a take of FF8iC "1" is input. In this way RDS p)
If the value exceeds 1, an erroneous detection signal is generated.

In addition, if you want to double the range of θ1 constant, use the U-D counter 6.
The output terminals Q+, Qt, Qs are the input terminal S of the selector. This is possible by connecting to +81 +82.

Also, the output terminal Q of the U-D counter 6. No matter what the initial value output from Q+Qt is, the center value of JRDS will be set to 3 and 4d in the above explanation immediately after the start of operation due to the above hold operation.
The value will be between.

(g) Effects of the Invention As explained in detail above, according to the present invention, even if the bit rate of the transmission signal reaches 100 Mb/see K, the U.1 counter, selector, FF, NOR circuit, Since the circuit uses 4'f[, the slope can be used even if the bit rate of the transmission signal becomes 100 Mb/see.
This has the effect of providing a signal error detection circuit.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional code error detection circuit, and Figure 2 is a block diagram of a conventional code error detection circuit.
The figure is a block diagram of a code error detection circuit according to an embodiment of the present invention.

Claims (1)

[Claims] In a sign@false code detection circuit that determines that a code word has occurred when the running digital sum exceeds a predetermined range,
When the data °l 01+ ++ 1°゛ is input
An up/down counter that counts up and inputs the count value to the selector, a selector that sets the predetermined range and outputs a limit signal when the input count value exceeds the predetermined range, and the limit Ig. If data that causes the count value of the up/down counter to fall outside the predetermined range is input, an error detection signal (a) is output and the up/down counter continues counting until data that makes the count value (a) fall within the predetermined range is input. 1. A code error detection circuit comprising means for holding the code.