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JPS6010752A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Semiconductor integrated circuit device and manufacture thereof

Info

Publication number
JPS6010752A
JPS6010752A JP58119136A JP11913683A JPS6010752A JP S6010752 A JPS6010752 A JP S6010752A JP 58119136 A JP58119136 A JP 58119136A JP 11913683 A JP11913683 A JP 11913683A JP S6010752 A JPS6010752 A JP S6010752A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
semiconductor integrated
utilized
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58119136A
Other languages
Japanese (ja)
Inventor
Hiroshi Ishioka
石岡　浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58119136A priority Critical patent/JPS6010752A/en
Publication of JPS6010752A publication Critical patent/JPS6010752A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/45124—Aluminium (Al) as principal constituent
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48717—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48724—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve the moisture proof of the title device by a method wherein an insulating film is provided on the surface of a metallic wiring layer which is not covered with a passivation film and not coming into contact with bonding wire. CONSTITUTION:A base ribbon utilized for a plastic package is formed of an island 1 and multiple external terminals 2 peripherally connected to one another. Besides the base ribbon is mostly made of iron and nickel alloy while a metallic wire is utilized for a bonding wire 9. Aluminium utilized for a wiring 5 is more easily ionized than any metals utilized for the base ribbons 1, 2 and the bonding wire 9. Therefore, when a semiconductor integrated circuit device is immersed in electrolyte after eompletion of bonding process for anodic oxidation utilizing the base ribbons as anode, the aluminium surface exposed on IC element is oxidized into alumina 10. Through these procedures, the title device may prevent aliminium corrosion from happening and improve the moisture proof thereof.

Description

【発明の詳細な説明】 本発明は、半導体集積回路装置（以下ＩＣという）およ
びその製造方法Ｋかかシ、と〈Ｋ耐湿性が向上ＩＣおよ
びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device (hereinafter referred to as an IC) and a method for manufacturing the same, an IC with improved moisture resistance, and a method for manufacturing the same.

プラスチックパッケージがＩＣの封止材料として広範囲
に使用されるにつれてＩＣ素子の耐湿性向上が重要な問
題となっている。これは封止用のプラスチック樹脂は気
密封止用のセラミックや金属と異なシ本戸的に水を通す
ため、侵入した水分が配線材料のアルミｅ腐食させ、ア
ルミ配線の断線を引き起すためである。ＩＣ素子の表面
は一般にアルミ配線上にパッシベーション膜をかぶせて
侵入した水分とアルミ配線とが接触しないようＫしてい
るが、このパッシベーション膜にクラック（ひび割れ）
やピンホールなどがあるとそこからアルミの腐食が発生
する。さらにＩＣ素子とパッケージの端子とを接続する
ためのポンディングパッドにはパッシベーション膜をか
ぶせていないためアルミの腐食が発生してしまう。パッ
ジページ舊ン膜のクラックやピンホールはパッジベージ
ｌン膜の材質や被着方法を改善する事で発生を低減する
事は可能であるが、ポンディングパッド部は必然的にむ
き出しのアルミが出てしまう事になる。As plastic packages are widely used as encapsulating materials for ICs, improving the moisture resistance of IC devices has become an important issue. This is because plastic resin for sealing is different from ceramics and metals for airtight sealing, and because it allows water to pass through, the moisture that enters corrodes the aluminum wiring material, causing the aluminum wiring to break. be. Generally, the surface of an IC element is protected by covering the aluminum wiring with a passivation film to prevent intruding moisture from coming into contact with the aluminum wiring, but this passivation film may crack.
If there are holes or pinholes, corrosion of the aluminum will occur from there. Furthermore, since the bonding pads for connecting the IC element and the terminals of the package are not covered with a passivation film, corrosion of the aluminum occurs. It is possible to reduce the occurrence of cracks and pinholes in the pad page membrane by improving the material and adhesion method of the pad page membrane, but exposed aluminum inevitably appears in the bonding pad area. It will end up happening.

本発明はこれらの問題点を解決し、耐湿性を向上させた
半導体集積回路装置およびその製造方法を提供するもの
である。The present invention solves these problems and provides a semiconductor integrated circuit device with improved moisture resistance and a method for manufacturing the same.

本発明の特徴は、半導体基板と、その−主表面上に設け
られた半導体素子と、この素子間を接続する金属配線層
と、−主表面を覆うバッシペーシヲン膜トを有するＩＣ
Ｅおいて、パッシベーション膜に覆われておらず、かつ
ボンディング線と接触していない金属配線層の表面に絶
縁膜を設けたＩＣにある。The present invention is characterized by an IC having a semiconductor substrate, a semiconductor element provided on its main surface, a metal wiring layer connecting these elements, and a bassine film covering the main surface.
E is an IC in which an insulating film is provided on the surface of a metal wiring layer that is not covered with a passivation film and is not in contact with a bonding line.

又、本発明の他の特徴は、ボンディングが完了したＩＣ
のケース端子又はベースリボンを電極として、露出した
金属配線層表面の陽極酸化を行う工程と、その後で封入
を行う工程とを含むＩＣの製造方法にある。Another feature of the present invention is that the IC with completed bonding
The method of manufacturing an IC includes the steps of anodizing the exposed surface of the metal wiring layer using the case terminal or base ribbon as an electrode, and then encapsulating the surface of the metal wiring layer.

以下実施例に基づき本発明の詳細な説明する。The present invention will be described in detail below based on Examples.

第１図はボンディング工程が完了した半導体集積回路装
置を模式的に表わしたものであって、１はＩＣ素子をマ
ウントしたアイランド部、２はケースの端子部分、３は
シリコン基板、４は拡散層、５はポンディングパッドお
よびそれにつながるアルミ配線このうち５′がポンディ
ングパッド、６は内部のアルミ配線、７はパッシベーシ
ョン膜、８ハハツシベーシヨン膜に生じたクラック又は
ピンホール、９はボンディング線を表わす。FIG. 1 schematically shows a semiconductor integrated circuit device after the bonding process has been completed, in which 1 is an island portion on which an IC element is mounted, 2 is a terminal portion of a case, 3 is a silicon substrate, and 4 is a diffusion layer. , 5 is a bonding pad and aluminum wiring connected to it, 5' is a bonding pad, 6 is an internal aluminum wiring, 7 is a passivation film, 8 is a crack or pinhole that occurs in the hatching film, 9 is a bonding line represents.

プラスチヅクパッケージで用いるベース、リボンは、ア
イランド１と複数ある外部端子２はすべて周囲でつなが
って形成されている。また、ペースリボンは鉄とニッケ
ルの合金で作られている事が多く、ボンディング線９に
は金線が使用される。The base and ribbon used in the plastic package are formed with an island 1 and a plurality of external terminals 2 all connected around the periphery. Further, the pace ribbon is often made of an alloy of iron and nickel, and the bonding wire 9 is made of gold wire.

配線５に使用されるアルミニウムは、ペースリボン１，
２及びボンディング線９に使用される金属のどれよシも
イオンイヒ傾向が大きい。従ってボンディング工程が終
了した段階で半導体集積回路装置を電解液中に浸し、ペ
ースリボンを陽極として陽極　１酸化を行なうと、ＩＣ
素子上の露出したアルミ表面が酸化されアルミナ（Ａｆ
Ｌ２０３　）　ｔｏ　Ｋ変わる（第２図）。すなわち、
クラック、ピンホール８内の表面や、ポンディングパッ
ド５′内でボンディング線９がボンディングされていな
い表面がアルミナ膜１０に変わる。Ｎチャネルシリコン
ゲートのＭＯ８型集積回路を例にとると、外部端子２か
ら直接に電圧を印加されるポンディングパッドのアルミ
表面はもちろん、シリコン基板３（Ｐ型）から拡散層４
（Ｎ＋型）へと電流が流れ、拡散層と接続されている内
部のアルミ配線にも電圧が印加されるため、内部配線上
で発生したクラックやピンホールによって露出したアル
ミ表面をも、アルミナ膜に変える事が出来る。The aluminum used for the wiring 5 is the pace ribbon 1,
All of the metals used for the bonding wires 2 and 9 have a greater tendency to ionize. Therefore, when the semiconductor integrated circuit device is immersed in an electrolytic solution after the bonding process is completed and anode oxidation is performed using the paste ribbon as an anode, the IC
The exposed aluminum surface on the element is oxidized and becomes alumina (Af).
L203) to K changes (Figure 2). That is,
The surfaces inside the cracks and pinholes 8 and the surfaces within the bonding pads 5' to which the bonding wires 9 are not bonded turn into an alumina film 10. Taking an N-channel silicon gate MO8 type integrated circuit as an example, not only the aluminum surface of the bonding pad to which a voltage is directly applied from the external terminal 2, but also the diffusion layer 4 from the silicon substrate 3 (P type)
(N+ type), and voltage is also applied to the internal aluminum wiring connected to the diffusion layer, so the aluminum surface exposed by cracks and pinholes generated on the internal wiring is also covered by the alumina film. You can change it to

陽極酸化を行なう際の電圧および電流値の設定条件によ
ってはできたアルミナ膜が多孔質になる事があるため、
適正条件を設定する必要がある。Depending on the voltage and current settings during anodization, the resulting alumina film may become porous.
It is necessary to set appropriate conditions.

この後にプラスチック封止全行なってリードを切断し整
形して製品とするが、プラスチック樹脂を通って侵入し
た水分はむき出しのアルミに接する事がないのでアルミ
腐食による断線不良の発生を防ぐ事が出来る。After this, all the plastic sealing is done, and the leads are cut and shaped to make the product, but since moisture that has entered through the plastic resin does not come into contact with exposed aluminum, it is possible to prevent disconnection defects due to aluminum corrosion. .

５　− 以上詳細に説明したように本発明はボンディング完了時
に露出しているアルミ配線パターン表面をアルミナ膜（
ＡＩ１２０３）に変える事によシアル之腐食の発生を防
ぎ、耐湿性を向上させるものである。5 - As explained in detail above, the present invention covers the exposed aluminum wiring pattern surface upon completion of bonding with an alumina film (
By changing to AI1203), the occurrence of sial corrosion is prevented and moisture resistance is improved.

尚、本発明は上記実施例に限らず、たとえば金属配線が
外部端子と電気的に直接、または間接に接続されている
構造の素子に広く適用することができる事は言うまでも
ない。It goes without saying that the present invention is not limited to the above-mentioned embodiments, but can be widely applied to elements having a structure in which, for example, metal wiring is electrically connected directly or indirectly to an external terminal.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はボンディング完了後の半導体集積回路装置を模
式的に表わした図面である。第２図は本発明の実施例に
おいて、陽極酸化を＃１どこしたあとの半導体集積回路
装置を模式的に表わした図面である。 尚、それぞれの図面において、１・・・・・・ＩＣ素子
をマウントしたアイランド部、２・・・・・ケースの外
部端子−につながるリード線、３・・・・・シリコン基
板、４・・・・・・拡散層、５・・・・・・ポンディン
グパッドとそれにつ６一 々がるアルミ配線（このうちぎがポンディングパッド）
、６・・・・・・内部のアルミ配線、７・・・・・・パ
ッシベーション膜、８・・・・・・パッジベージ１ン膜
に生じたクラック又はピンホール、９・・・・・・ボン
ディング線、１０・・・・・・陽極酸化によってできた
アルミナ膜、を表わす。 ７−FIG. 1 is a drawing schematically showing a semiconductor integrated circuit device after completion of bonding. FIG. 2 is a drawing schematically showing a semiconductor integrated circuit device after anodization #1 in an embodiment of the present invention. In each drawing, 1...the island portion on which the IC element is mounted, 2...the lead wire connected to the external terminal of the case, 3...the silicon substrate, 4...・・・Diffusion layer, 5...Ponding pad and 6 aluminum wiring connected to it (this one is the bonding pad)
, 6... Internal aluminum wiring, 7... Passivation film, 8... Cracks or pinholes generated in the padding film, 9... Bonding Line 10 represents an alumina film formed by anodic oxidation. 7-

Claims (2)

【特許請求の範囲】[Claims] （１）半導体基板と、その−主表面上に設けられた半導
体素子と、該素子間を接続する金属配線層と、該主表面
を覆うパッシベーション膜とを有する半導体集積回路装
置において、前記パッシベーション膜に覆われておらず
、かつボンティング線と接触していない金属配線層の表
面に絶縁膜を設けた事を特徴とする半導体集積回路装置
。(1) In a semiconductor integrated circuit device having a semiconductor substrate, a semiconductor element provided on the main surface thereof, a metal wiring layer connecting the elements, and a passivation film covering the main surface, the passivation film 1. A semiconductor integrated circuit device characterized in that an insulating film is provided on the surface of a metal wiring layer that is not covered with bonding wires and is not in contact with bonding wires. （２）ボンディングが完了したケース端子又はペースリ
ボンを電極として、露出した金属配線層表面の陽極酸化
を行う工程と、その後で封入を行う工程とを含むことを
特徴とする半導体集積回路装置の製造方法。(2) Manufacture of a semiconductor integrated circuit device characterized by including a step of anodic oxidation of the surface of the exposed metal wiring layer using the bonded case terminal or paste ribbon as an electrode, and a step of subsequent encapsulation. Method.
JP58119136A 1983-06-30 1983-06-30 Semiconductor integrated circuit device and manufacture thereof Pending JPS6010752A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58119136A JPS6010752A (en) 1983-06-30 1983-06-30 Semiconductor integrated circuit device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58119136A JPS6010752A (en) 1983-06-30 1983-06-30 Semiconductor integrated circuit device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS6010752A true JPS6010752A (en) 1985-01-19

Family

ID=14753824

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58119136A Pending JPS6010752A (en) 1983-06-30 1983-06-30 Semiconductor integrated circuit device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS6010752A (en)

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