JPS6010741A - Inspection of semiconductor nonvolatile memory device - Google Patents

Abstract

PURPOSE:To enable to perform the inspection of memory holding inferiority of an MOS memory device (memory) in a short time by a method wherein after a semiconductor chip is controlled in a high temperature atmosphere in a wafer condition as it is, the prescribed informations are read out. CONSTITUTION:After informations are written according to electric charge implantation to a semiconductor nonvolatile memory device in a wafer condition, holding defective units are removed utilizing thermal stress applied according to control in a high temperature atmosphere. Namely, at electric tests of respective chips in the wafer condition, the prescribed data are written. The chips are controlled in a high temperature condition in a baking oven set at the prescribed temperature at wafer baking. Then the data written at the former electric tests are read out at an electric test, and marks to indicate inferiority are printed to the chips having uncoincident data.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for testing a semiconductor non-volatile memory device, and in particular to a method for testing a semiconductor non-volatile memory device.
The present invention relates to a method for inspecting memory retention defects in a storage device (memory).

First, the configuration and operation of a semiconductor nonvolatile MOS memory will be explained. Figure 1 shows FAMO8 (Floa-ting-g), which is a type of semiconductor non-volatile MOS memory.
ate Avalanche 1 injection M
etalOxide Sem1conductor)
) is a vertical cross-sectional view showing the configuration of a transistor; In FIG. 1, 1 is a semiconductor substrate, 2 is a substrate terminal attached to the semiconductor substrate 1, and 3@4 is an impurity diffusion region of a conductivity type opposite to that of the substrate 1, forming a source region and a drain region, respectively. 596 is a metal conductor that is in ohmic contact with the source region 3 and drain region 4, respectively; 7 and 8 are source and drain terminals that are connected to the metal conductors 5 and 6, respectively; 9 is provided within the gate oxide film 13 and is electrically 10 is a floating gate located on top of the floating gate 9 via a gate oxide film 13; 11 is a control gate; The ohmic contact metal conductor 12 is a control gate terminal connected to the metal conductor 11.

In this FAMO8) transistor, the current flowing between the source region 3 and drain region 4 is con).

- controlled by the voltage applied to the floating gate terminal 12 and the potential of the floating gate 9.

Here, the potential of floating gate 9 is determined by the charge stored in floating gate 9. Since this floating gate 9 is completely surrounded by gate oxide, which is an insulator, this charge remains even when the power to the external circuit is turned off, and ideally it is stored permanently. . Therefore, the presence or absence of this charge is made to correspond to the binary logic 1"1m, II□I+, and is used as a nonvolatile memory.

In actual semiconductor non-volatile storage devices, the memory and
Transistors are manufactured in the order of several thousand to hundreds of thousands, and for each memory transistor shown in FIG. 1, charge exists in the fleeting gate 9 and charge does not exist. Things are in a mixed state. As mentioned above, in such a nonvolatile semiconductor device, the potential of the floating gate 9 should remain unchanged under ideal conditions, but for some reason, charges may be injected into the floating gate 9 or the floating gate 9 may be injected. gate 9
This floating gate 9
The potential of changes. The smaller this variation, the greater the memory's retention capacity, but it takes an extremely long time under actual usage conditions to inspect memory with defective memory retention. For this reason, special heat aging that lasts a relatively long time is required to inspect for defective products, which poses a major hindrance to production.

The object of the present invention is to provide an inspection method that solves these problems.

A feature of the present invention is that a semiconductor non-volatile memory device in a wafer state removes defective products by utilizing thermal stress applied by storing the device in a high-temperature atmosphere after information is written to the semiconductor non-volatile memory device by charge injection. There is a memory retention test method.

That is, after predetermined information is written in a semiconductor nonvolatile memory device in the form of a wafer, thermal stress is applied to the wafer by storing it in a high temperature atmosphere. This is an inspection method in which the previously written information is read again from the semiconductor nonvolatile memory device in the wafer state after storage and a semiconductor nonvolatile memory device that does not match the written information is determined to be defective in memory retention.

Examples of the present invention will be described below. FIG. 2 shows an embodiment of the manufacturing process according to the present invention. During the manufacturing process in Figure 2 [F
] Predetermined data is written in the electrical test of each chip in the wafer state indicated by the arrow. The one indicated by the arrow ■,
- Store at a high temperature in a baking oven set at a predetermined temperature. In the electrical test indicated by the arrow ■, mark 7 as indicated by the arrow ■ indicates that the data written in the electrical test is discarded, and the chip whose read data does not match is marked as defective.

Table 1 shows reliability test results using semiconductor nonvolatile memory devices manufactured using the manufacturing process according to the present invention. The purpose of this test is to confirm the effects of the present invention. In the test results shown in Table 1, no defects occurred, and the present invention was extremely effective. 5-

[Brief explanation of the drawing]

FIG. 1 is a longitudinal cross-sectional view of the FAMO8 structure, and FIG. 2 shows the manufacturing process of the semiconductor nonvolatile memory device. In the same figure, 1.1...semiconductor substrate, 2...
・・・Board terminal that makes ohmic contact with semiconductor, 3
, 4... Impurity diffusion region of conductivity type opposite to that of the substrate, 5.6... Metal conductor making contact with the impurity diffusion region in an orderly manner, 7. Death: terminal connected to metal conductor, 9: fluted gate, 1
o...Control-gate, 11...
・Metal conductor that makes ohmic contact with the control gate, 12. Old... Terminal connected to the metal conductor, 13.
...layer insulating gate oxide film, substrate, fleeting gate, control gate, etc., 14...
...field oxide 6- film, an insulating isolation region between adjacent elements. -7- 27 Figure 2 Figure Buddhist monk〕L Assembly process-

Claims (1)

[Claims] A method for testing a semiconductor non-volatile memory device, characterized in that predetermined information is written in a semiconductor chip in a wafer state, the semiconductor chip is stored in a high temperature atmosphere in a wafer state, and then the predetermined information is read out. A method for testing non-volatile storage devices.