JPS6010457B2 - Microprocessor controlled PLL - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprocessor-controlled PLL' that performs feedback control to change the oscillation frequency according to the phase difference between input and output under the control of a microprocessor. .

A PLL (phase locked loop) performs feedback control to keep the oscillation frequency of the voltage controlled oscillator VCO constant by changing the oscillation frequency of the voltage controlled oscillator VCO according to the phase difference between input and output. It is used for the purpose of obtaining an oscillation frequency signal that follows.

FIG. 1 is a block diagram showing the configuration of a conventional PLL.

In the figure, 1 is a voltage controlled oscillator (VCO) that oscillates and outputs a signal with a frequency corresponding to an input voltage.

Phase comparator 2 detects the phase of the VCO output signal. and reference input signal phase i to generate an output according to the phase difference.
This phase difference signal passes through a low frequency filter (LPF) 3 to remove high frequency components, and is then fed back to the VCOI to change its oscillation frequency. As a result of feedback control being performed in this manner, the oscillation output signal phase of the VCOI is controlled to match the input signal phase. However, in such conventional PLL's, it is not only impossible to easily change the characteristics of the feedback control loop that constitutes the PLL, such as the loop gain, but also difficult to realize a highly stable VCO. Therefore, it has been difficult to construct a PLL with sufficient control accuracy.

The present invention attempts to eliminate such drawbacks of the prior art, and its purpose is to increase the input clock outside the counter that divides the oscillation output signal of the Fuji oscillator according to instructions from the microprocessor. , or a PLL that can configure a feedback control loop by controlling the phase at the counter output by decreasing it, and thereby perform high-precision control based on desired characteristics.
Our goal is to provide the following. To achieve this objective, the microprocessor-controlled PLL of the present invention includes means for generating a fixed frequency signal, a first counter that counts the fixed frequency signal and generates a carry output at every fixed count; a second counter that divides the output signal of the first counter, detects a phase difference between the output signal of the second counter and the input signal, and obtains a value according to the yield phase difference for each input signal pulse; and a microprocessor that determines whether the frequency of the input signal of the first counter should be increased or decreased. Based on the determination result of the microprocessor,
gate means controlled to add one pulse between the input pulses of the first counter or to block one input pulse; The present invention is characterized in that the number of times the gate means is controlled in relation to the number of carry outputs of the counter is determined and the output signal phase of the second counter is controlled to follow the input signal phase. Examples will be described below.

FIG. 2 is a block diagram showing the configuration of one embodiment of the microprocessor can LL of the present invention. FIG. 3 is a time chart showing the operation waveforms of each part in FIG. 2.

In Figure 2, Tomomi is a fixed frequency oscillator, blade 2 is an input terminal, turtle 3 is a frequency divider by 2 (IJ2), 146 is an inhibit circuit, turtle 5 is an AND circuit, turtle 6 is an OR circuit.
IT is a boot counter, 1 is an n-ary counter, 19 is an output terminal, 2 is a rise detection circuit for 28G, 2 is a flip-flop, 22 is an interrupt bus, 3 is a microprocessor,
24 is an N-ary down counter, 26 is a register, crab 6 is a data bus, 2 is an address bus, 2 is a decoder, 3 is a flip-flop, 38 is an AND circuit, 3W is a flip-flop, and 32 is an AND circuit. Funama inhibit circuit ``3& is an AND circuit.

In Figure 2, ``Toyama is a fixed frequency oscillator with high stability, such as a crystal oscillator, and its oscillation frequency is 2hnfo (m'' where n is positive), where fo is the input signal frequency at input terminal 2. ).

In FIG. 3, a indicates the output signal 2hn of the fixed frequency oscillator 11. The output signal of the oscillator 11 is applied to a frequency divider (1/2) 13 and frequency-divided by 2 to produce two signals having a 180° phase difference. In FIG. 3, b and c are signals, respectively, and indicate J2. In the signal ◇・, 2 passes through the inhibit circuit 14, the AND circuit 15, and the OR circuit 16, and normally becomes the signal ? , is selected and added to the m-ary counter 17, and is divided by m to obtain the frequency mo
generates a signal. This signal is further applied to an n-ary counter 18 and divided by n to produce a signal of 0 frequency. This signal is output to output terminal 19. The rising edge of the input signal fo applied to the input terminal 12 is detected by the rising edge detection circuit 20, and a flip-flop 21 is set for each output.

The output signal of flip-flop 21 interrupts microprocessor 23 via interrupt bus 22. The microprocessor 23 has an AND circuit 3 on the address bus in order to specify the AND circuit 34 when an interrupt is generated.
4 address signal is loaded. The decoder 28 decodes the address signal on the address bus, sends out a signal to open the AND circuit 34, and inputs the count value of the n-ary counter 18. This increases the amount by which the frequency should be changed and the frequency. Determine whether the amount should be increased or decreased.
Then, the amount by which the frequency should be changed is determined by an N-ary down counter 24
Also writes a plus or minus to the register SI depending on whether the frequency is to be increased or decreased. Writing of these data is performed through the data bus 28, and address designation is performed through the address bus and through the decoder 2 groove. When the base is set, the output signal n of the m-adic counter Fuki is inputted to the N-adic down counter rate via the toand circuit 30 to start counting.

On the other hand, the flip-flop 8 has an output of 2 frequency divider quantity 3,
It is reset every time the output is output, so the output is in the state of 0 seconds.

In this state, the outputs of the AND circuit field 2 and the inhibit circuit 3 are both G'07', and the signal &, is input to the m-adic counter field 7 through the inhibit circuit Kamikame, and the output of the shoemaking counter field is G'07'. 7 carries carry output nf for every m counter.
o (shown in FIG. 3d) and flip-flop 3
Set to 1. Now, assuming that registers 2 and 5 are set to positive and their output is "1", the setting of flip-flop 31 causes the output to pass through AND circuit 32 and open AND circuit 15, thereby causing signal ◇
The pulse of 2 passes through the OR circuit 16 only once and is input to the m-adic counter 17.

In FIG. 3, d indicates the output nfo of the m-ary counter 17, and e indicates the operation of the flip-flop 31 based on the output Mo. As a result, f passes through the OR circuit 16 and becomes m
The signal input to the digit counter 7 is shown. Assuming that the register 25 is set to a negative value and its output is "0", the setting of the flip-flop 31 causes its output to pass through the inhibit J circuit 33 and close the inhibit circuit 14, thereby causing the signal ? The pulse of , is 1
blocked only once.

In FIG. 3, g indicates the output mo of the m-adic counter 17, and h indicates the operation of the flip-flop 31 based on the output nfo. By this, i passes through the OR2 circuit 16 and m
A signal input to the advance counter 17 is shown. In this way, the output of register 25 becomes "1"?
It changes by m depending on whether it is 0'' or not.

Such an operation is repeated every time a carry output is generated from the m-ary counter 17, and at the same time, the N-ary down counter 24 is counted down and the flip-flop 29 is
Reset. As a result, the AND circuit 306 is closed, and the output of the flip-flop 31 becomes ``0'', the AND circuit 32 and the inhibit circuit 33 are both closed, and the change in the output frequency of the m-ary counter 171 is stopped. Whether this operation is performed for each period of the output signal fo is determined by the initial value finally set in the N-ary down counter 2 as described above.Now, each time the input signal fo is input to the terminal 2, the flip-flop 2 is set If the value written to the N-ary down counter 24 is K, then either "1" is set in the register 25 or "0" is set in the register 25.
is set, the output frequency fo' at the terminal 19 is expressed by the following formula '1 or [21], respectively.

Nikizo f.

3 (10 lanes) f.

（・）Kem mother magazine f.

3(・-potato) f.

(2) However, in either case, m・n》K.

In this case, the jusai circle at terminal 12. The phase difference between the output signal and the output signal at the terminal 19 is obtained by calculating the count value of the n-ary counter 18 when the input signal is applied. For example, when a signal is input and it is desired to output a signal at a phase such that the count value of an n-ary counter becomes a ratio, let A be the phase difference, and the phase difference Δ is expressed by a linear equation. △
(3)nwhere n is the count value of the n-ary counter when the input signal is added.

A PLL can be configured by determining the set value K for the N-ary down counter 24 and the polarity for the register 25 in accordance with the thus determined phase difference Δ.

As explained above, the microprocessor control P of the present invention
According to the LL, it is possible to configure a PLL that controls the phase of the counter output by increasing or decreasing the input clock in the counter that divides the oscillation output signal of the original oscillator under the control of the microprocessor. It is possible to realize a PLL that can perform highly accurate control based on the characteristics.

[Brief explanation of drawings]

Figure i is a block diagram showing the configuration of a conventional PLL, Figure 2 is a block diagram showing the configuration of an embodiment of the microprocessor control unit LL of the present invention, and Figure 3 is the operating waveform of each part in Figure 2. It is a time chart showing. Tortoise... Voltage controlled oscillator (VCO), 2... Phase comparator ~ 3... Low frequency filter (LPF), 11... Fixed frequency oscillator, No. 2... Input terminal, S3... 2 frequency divider (
1〆2) "14...Inhibit circuit ~ 15...
... Asodo circuit " 16 ... OR circuit, turtle 7 ... m-ary counter " 8 ... n-ary counter, 19 ... output terminal, 28
... Rise detection circuit, 21 ... Flip-flop, 22 ... Interrupt bus, 23 ... Microprocessor, 24 ... N-ary down counter, 25 ... Register "26 ... Data bus "27 ...Address bus "28...
...Decoder, 29...Flip-flop, 30...'
AND circuit, 31...Flip-flop, 32
......AND circuit, 33...Inhibit circuit, 34......AND circuit. Oh figure soup figure 2 figure 3

Claims (1)

[Claims] 1. Means for generating a fixed frequency signal, a first counter that counts the fixed frequency signal and generates a carry output every fixed count, and a second counter that divides the output signal of the first counter. , the phase difference between the output signal and the input signal of the second counter should be detected and a value corresponding to the phase difference should be obtained for each input signal pulse, and the frequency of the input signal of the first counter should be increased. a microprocessor for determining whether the counter should increase or decrease; and gate means controlled to add one pulse between the input pulses of the first counter or to block one input pulse depending on the determination result of the microprocessor. and determining the number of times the gate means is controlled for the number of carry outputs of the first counter based on the value determined by the microprocessor, and controlling the output signal phase of the second counter to follow the input signal phase. A microprocessor controlled PLL characterized by: