JPS60103454A - Instruction pre-reading controller - Google Patents

Abstract

PURPOSE:To eliminate the waiting control for initialization by using an instruction selector which transfers the data addressed by an address register AR directly to an instruction register and a data bus which transfers the contents of the AR to pre-fetching register. CONSTITUTION:When a branch instruction is transferred to an instruction register IR5, a branching destination address is calculated by an operator 9. Thus calculated value is transferred to an AR2 to start an input action for the data on the address designated by the AR2. In this case, the storing destination of data is headed directly toward the IR5 via an internal bus 11. While a micro- code for execution of a normal input/output action is delivered to a microinstruction register 7 for execution of the data input action. A decoding signal F of the microcode is used for control of a buffer 12, an instruction selector 14 and an address selector 3 respectively. For the next instruction of the head address of the branching destination, the contents of the AR2 are sent to a pre- fetching register 1 via a data transfer bus 13 and in parallel to the data transfer cycle to the IR5 since a pre-reading action is performed by the register 1.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an instruction prefetch control device constituting a data processing device.

Conventional configurations and their problems In recent years, data processing devices have built-in various advance control devices to improve processing speed. It is expected to be very effective and is being incorporated not only in large-scale computers but also in microprocessors.

A conventional instruction prefetch control device will be described below. FIG. 1 shows a configuration diagram of a conventional instruction prefetch control device, in which 1 is a prefetch register that holds an instruction prefetch address, 21 is an address register that holds addresses other than the instruction read address, 3 is an address selector,
4 is an instruction queue for storing prefetched instructions; 6 is an instruction register for storing instructions retrieved from the instruction queue 4; 6 is a now microcontroller that controls the execution of instructions according to the contents of the instruction register 5; 7 is a microcontroller 6 8 is a decoder that decodes the contents of the microinstruction register and sends signals necessary for control; 9 is an arithmetic unit;
1o is an external bus that is directly connected to the instruction queue 4; 11 is an internal bus that is used to transfer the results of the arithmetic unit to the prefetch register 1 and the address register 2; This is a buffer provided to disconnect the external bus 1o and the internal bus 11 when they are executed simultaneously.

Further, A is a control signal that controls the address selector 3 and makes the output of the address register 2 the output of the selector 3, B is a control signal that stores data in the brief fetch register 1,
C is a control signal that transmits the state of the brief fetch register 1 to the microcontroller 6, D is a control signal that stores data from the instruction queue 4 in the instruction register 5, and E is a control signal that transmits the state of the instruction queue to the microcontroller 6. It is a control signal.

The operation of the conventional one-money order look-ahead control device configured as described above will be described below.

First, the prefetch register 1 updates the prefetch address independently of the operation of the internal arithmetic unit 9, outputs this address through the selector 3, and stores the instructions at this address one after another in the instruction queue via the external bus 10. . The microcontroller 6 operates on the premise that instructions are always prepared in the instruction queue 4 and transferred from the instruction queue 4 to the instruction register 5 as instructions are consumed by the microcontroller 6. Therefore, the instruction lookahead time is
This is hidden in the execution time of the instruction, and the processing speed can be improved. However, in the above configuration, when executing a branch instruction, in the process of canceling the instruction queue and storing the branch destination address in the pre-fetch register 1, the data storage control signal B to the pre-fetch register 1 is sent to the pre-fetch register 1. 1 to the microcontroller 6, which indicates that the pre-fetch register 1 is operating, and the storage control signal B must be sent while the pre-fetch register 1 is stopped. No.

Furthermore, when storing an instruction from the instruction queue 4 to the instruction register 6, the instruction queue 4 is canceled and the instruction corresponding to the address newly stored in the brief fetch register 1 is output from the instruction queue 4 until it is stored. Due to the control signal E, the instruction register 5 cannot be stored until the control signal E is no longer output. It is necessary to incorporate various types of complicated waiting control circuits such as
timing of initialization of the register, i.e., the initialization timing of the register 1
The timing of rewriting and canceling the instruction queue 4 cannot be displayed on the peripheral device in synchronization with the instruction read cycle, which has the disadvantage that the interface of the peripheral device becomes complicated.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional problems, and eliminates complicated waiting control in the initialization of an instruction prefetch device in branch instruction processing, and also adjusts the initialization timing, that is, the rewrite timing signal of the prefetch register, to the instruction readout. An object of the present invention is to provide a prefetch control device that can easily output instructions to a peripheral device in synchronization with a cycle.

Structure of the Invention The instruction prefetch control device of the present invention includes a brief fetch register that holds an instruction prefetch address, an address register that holds an address for data transfer other than the instruction prefetch address, and an address selector that receives the outputs of the two registers as inputs. an instruction queue that stores instructions read out according to the address of the pre-7 etch register; an instruction selector that receives the instructions output from this instruction queue and the instructions read out from the address register; The device is equipped with an instruction register for storing data, a means for reading and writing data to the address register, and a means for transferring the contents of the address register to the brief fetch register, and when a branch instruction is executed, the address register is selecting the output with the address selector and selecting the read instruction with the instruction selector;
A control signal for instructing storage in the instruction register can be output in an instruction read data transfer cycle.

DESCRIPTION OF THE EMBODIMENT FIG. 2 shows a configuration diagram of an instruction prefetch control device in an embodiment of the present invention.

In FIG. 2, 1 is a prefetch register that holds the instruction prefetch address, 2 is an address register that normally holds addresses other than the prefetch address, 3 is an address selector, and 4 is a prefetch register that stores the instruction read by the prefetch register. 5 is an instruction register that stores the output of the instruction queue 4 or instructions directly from the internal bus 12 (described later) via an instruction selector 14 (described later); 6 is an instruction register 7 that stores instructions according to the contents of the instruction register 6; 7 is a microinstruction register that stores the output of microcontroller 6; 8 is a decoder that decodes the contents of microinstruction register 7 and generates a control signal; 9 is an arithmetic operation 10 is an external bus for transferring instruction prefetch data, 11 is an arithmetic unit 9
12 is a buffer that disconnects the external bus from the internal bus so that instruction prefetch operations and arithmetic operations can be executed simultaneously; 13 is a buffer that is used to transfer the contents of address register 2 to address register 2, etc. 14 is an instruction selector which inputs the output of the instruction queue 4 and the data of the internal node 11 and sends the output to the instruction register.

Further, F is a control signal output from the decoder 8 in the operation of reading the first instruction of the branch destination address in execution of a branch instruction, and G is a first signal that controls the transfer of the contents of the address register 2 to the brifetch register 1. It is.

The operation of the instruction prefetch control device according to the embodiment of the present invention configured as described above will be described below.

The instruction prefetch operation of this device is carried out by the brief fetch register 1, independently of the arithmetic unit 9 on the internal bus 11 or the microcontroller 6.
Instructions are stored one after another through the key register 6
When an instruction other than a branch instruction is being transferred to the instruction queue 4, the microcontroller 6 transfers the instruction from the instruction queue 4 according to the execution of the instruction in the instruction register 5, that is, according to the consumption of instructions. Retrieval 7 command sector 14
is stored in the instruction register 5 via the instruction register 5. Therefore, the instruction prefetch time can be hidden in the instruction execution time. Next, when a branch instruction is transferred to the instruction register 6, the branch destination address is calculated using the arithmetic unit 9, this value is transferred to the address register 2, and the branch destination address is transferred to the address register 2. The input operation of data at the address specified by 2 is started. At this time, the data is stored directly in the instruction register 6 via the internal bus 11. In order to perform the above data input operation, a microcode for executing the input/output operation is outputted to the microinstruction register 7. The decode signal F of this microcode (microinstruction) is used to control the controller 12 (connecting the external bus 10 and internal bus 11) and to control (internal) bus 11 of the instruction selector 14 to the instruction register. turn to ) and controls the address selector 2. In order to cause the prefetch register 1 to prefetch the instruction following the branch destination first address, the contents of the address register 2 are transferred to the prefetch register 1 in parallel with the data transfer cycle to the second instruction register 6. It is sent using the transfer bus 13.

FIG. 3 is a timing diagram showing the control sequence of branch instruction execution in this embodiment, and shows that the first instruction at the branch destination address is directly stored in the instruction register via address register 2. There is.

As described above, according to the present invention, the instruction selector 14 directly transfers the data addressed in the address register 2 to the register register 2, and the data bus transfers the contents of the address register 2 to the brief fetch register 1. 13, it is possible to eliminate the initialization work of the instruction prefetching device in branch instruction processing, that is, the waiting control 11 in updating the prefetch register and canceling and filling the instruction queue, and the initial JUJ timing information of the device can be eliminated. can be sent to the peripheral device in synchronization with the read cycle of the first instruction at the branch destination address, making it possible to reduce the cost of the hardware of the instruction prefetch control device and the hardware of the peripheral device.

In the embodiment, a microcontroller is used as the controller 6 for decoding and executing instructions, but it goes without saying that it may also be a wired logic type controller that does not have a clear microcode.

Effects of the Invention The instruction prefetch control device of the present invention directly transfers the first instruction of the branch destination addressed in the address register to the instruction register. The instruction selector switches the instruction data to be transferred, and the instructions from the address next to the branch destination address are stored in the address register so that they can be prefetched by the briefetch register. By providing a data bus, it is possible to eliminate the rewriting of the brief fetch register associated with the initialization of the instruction lookahead device in branch instruction processing, and the complicated waiting control in canceling and filling the instruction queue. can be sent to the peripheral device in synchronization with the first instruction read cycle, reducing the hardware cost of the entire device, which has a great practical effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional instruction prefetch control device, FIG. 2 is a block diagram of an instruction prefetch control device in an embodiment of the present invention, and FIG. 3 is a block diagram of a control device in an embodiment of the present invention. FIG. 7 is a timing diagram showing a 7-can. 1...Briefetch register, 2...
Address register, 3...address selector,
4...Instruction queue, 6...Instruction register, 6...Microcontroller, 7...
...Microinstruction register, 8...Decoder,
9... Arithmetic unit, 1o... External bus, 1
1...Internal bus, 12...Buffer, 1
3...Data bus, 14...Instruction selector. Name of agent Compiled by patent attorney Toshio Nakao and one other person
1 Figure 2/

Claims (1)

[Claims] A prefetch register that holds an instruction prefetch address, an address register that holds an address for data transfer other than the instruction prefetch address, an address selector that receives the outputs of the prefetch register and the address register, and a readout function that uses the address of the prefetch register. an instruction queue that stores instructions output from the instruction queue; an instruction selector that receives instructions output from the instruction queue and instructions read by the address register; an instruction register that stores the output of this selector; and an instruction register that stores the output of the selector; The device further comprises reading and reading means, and means for transferring the contents of the address register to the prefetch register, and when a branch instruction is executed, the output of the address register is selected by the address selector, and the read instruction is transferred to the prefetch register. An instruction prefetch control device that selects a control signal selected by a selector and instructs the instruction register to be stored in the instruction register, and outputs the instruction H in a data transfer cycle by 4"j.