JPS60101950A - Integrated circuit - Google Patents

Abstract

PURPOSE:To widen as much the area to be used for signal wirings by forming the branching lines of power supply wiring up to each function cell to be used and separated from the power supply terminal but before the cells not to be used, on the occasion of wiring the power supply line and signal lines to a semiconductor substrate of the master slice method where the functions cells are araranged in the lines and columns. CONSTITUTION:On the occasion of providing the colmumns of cell 2 on the semiconductor substrate and thereby forming an IC of the master slice method, unused function cells 5, used function cells 4 and unused function cells 5' are sequentially arranged to the right and left from the center of substrate. Next, the power supply line 6 and signal line are wired on the substrate. In this case, the power supply branching line 6 to be usually provided up to the unused function cells 5' is stopped at the used function cells 4 and the branching line 6 is not extended thereto. Thereby, the wiring for power supply 6 is laid short and simultaneously the signal line is wired in the predetermined area with some margin.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to integrated circuits manufactured using master slices.

Conventionally, the power wiring of integrated circuits manufactured using master slicing is fixed wiring, and when wiring signal lines, There is a need to perform wiring so that there is no ν. In addition, in a master slice system collection 41''1 circuit, there are almost always unused functional cells at t, but since the X distribution is fixed, the unused functional cells are There is a squad wiring part.

For this reason, there was a drawback that when designing the signal frame, it had to be designed and constructed in such a way that it would not short-circuit even if it was connected to unnecessary unused functional cells. .

FIG. 1 shows a plan view of an example of a conventional master slice.

Functional cell rows 2 are regularly arranged on the corridor substrate 1. In each cell row 2, functional cells 3 are arranged in a regular manner.

FIG. 2 is an enlarged view of the functional cell row shown in FIG.

In FIG. 2, the shaded functional cells 4 indicate used functional cells, and the non-hatched functional cells 5 indicate unused units. In a master slice integrated circuit,
Use depending on the type of product being manufactured! Lead h18 to Shimadai 18
-b / layer 1 + ball 71 (A-Figure 3 is a partial plan view of a functional cell array with power supply wiring.

Power supply wiring 6 runs vertically from the power supply terminal to each functional cell column.

Formed laterally. As shown in the figure, the conventional power supply wiring is fixed wiring, and is distributed from the end used functional cell 5 to the unused functional cell 5'. Chill.

In this way, the power supply wiring to the unused functional cells must also be manufactured in such a way that the signal lines are not short-circuited, which has the drawback of complicating design and manufacturing.

An object of the present invention is to provide a master slice that eliminates the above-mentioned drawbacks, eliminates power wiring to unused functional cells as much as possible, increases the area available for signal wiring, and facilitates design and manufacturing. The purpose of the present invention is to provide an integrated circuit based on the method.

The integrated circuit of the present invention is an integrated circuit in which a master slice in which functional cells are arranged in rows and columns on a semiconductor substrate is wired with grid lines and signal lines, in which each branch line of the power supply wiring is located farthest from a power supply terminal. Each used functional cell is formed, and the unused functional cells located ahead of each used functional cell, which is the end of the power wiring, are not provided with a power wiring.

Next, an example of the thermal power of this defense will be explained using drawings.

FIG. 4 is a plan view of one embodiment of the invention.

is wired from the power source terminal (not shown in FIG. 71), and branched wires are wired to each used functional cell 4 that is farthest from the power source terminal. The power supply wiring l113I is not provided to the unused functional cell 5' which is further ahead of the used functional cell located at the end. The parts that were conventionally wired but are no longer wired according to the present invention are shown with broken lines. In this way, by eliminating power wiring to unnecessary parts, the wiring area can be increased accordingly. This surface (l゛) can be used for signal line wiring. By doing &! between signal lines in places where there is no power wiring, there is no need to worry about short circuits with FL, 1N, and source wiring. The advantage is that it is easy to set up and manufacture.

As explained in detail above, the present invention reduces the power supply wiring area by eliminating all unnecessary power supply wiring, and utilizes the vacant area 'f: signal line wiring and reduces the risk of short circuits. It has this effect.

[Brief explanation of the drawing]

FIG. 1 is a flat 1fti diagram of an example of a conventional master slice, FIG. 2 is a partially enlarged view of the functional cell array shown in FIG. 1, and FIG.
The figure is a partial plan view of a functional cell array provided with a power supply arrangement, and FIG. 4 is a plan view of an embodiment of the present invention. J... Semiconductor substrate, 2... Functional cell row, 3... Functional cell, 4... Used functional cell, 5... Not available. Functional cell used, 6... Power supply wiring.

Claims (1)

[Claims] In an integrated circuit formed by wiring a power supply line and a signal line to a master slice in which functional cells are arranged in rows and columns on a semicircular substrate, a valley branch line of the power supply wiring is located at each functional cell used farthest from the power supply terminal. 1. An integrated circuit characterized in that a power supply wiring is not provided in an unused functional cell located ahead of each used functional cell that is formed and serves as the termination of the power supply wiring.