JPS60101639A - Information arithmetic device - Google Patents

Abstract

PURPOSE:To reduce the number of signal lines among circuit units by dividing an information arithmetic device into circuit units and constituting each circuit unit with a register which stores bit data at bit positions having spaces equivalent to the number of circuit units and a selector which shifts and delivers the bit data. CONSTITUTION:LSIs 301-304 are individually one LSI and four units of this LSI are arranged to obtain 32 bits. The LSI301 consists of an 8-bit register 305 and a selector 306 which performs a byte shift. The input of the LSI301 contains eight signal lines 307 for writing to the register 305; while the output of the LSI301 contains eight signal line 308 for reading respectively. A signal line 309 decides a bit of the selector 306. So is with LSIs 302-304 respectively. Thus the number of signal lines is reduced among LSIs. This can reduce the number of input/ output signal lines for an LSI.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an information processing device composed of bit and slice LSIs, and particularly to an information processing device suitable for nX2 bit shifting.

[Background of the invention]

When the contents of the 32-bit register 101 as shown in FIG. 1 are shifted and read in byte units (8-bit units), shift patterns 102 to 105 are possible. 102-105 indicate 0, 1, and 2.3 byte shifts, respectively.

This shift circuit is a conventional bit slice LSI, 4
FIG. 2 shows the case where it is composed of two pieces. 1 LSI201
It consists of an 8-bit register 202 and a selector 203 that performs byte shifting. The input of this LSI 201 has a signal line 204 for writing to the register 202, and the output has a signal line 205 for reading.

The numbers on these signal lines indicate the pit position (0
; Least significant bit, 31; Most significant piton. In order to perform a byte shift, eight signal lines 206 to 208 are each input, and eight signal lines 209 are output.

Further, the signal line 210 determines which bits of the selector 203 are to be fully selected. Looking at the least significant bit (bit position, 0), for a 0-byte shift, the contents of the register 202 (bit position, 0), and for a 1-byte shift, the contents of the signal line 208 (bit position,
8) For a 2-byte shift, the signal line 207 (bit position ft., 16), for a 3-byte shift,
The signal ffM2O6 (bit position; 24) is the selector 2
Selected by 03, signal +ill! 205 is read out at pit position 0.

However, the conventional method has the disadvantage that there are many signal lines crossing between LSIs, as shown in FIG.

[Purpose of the invention]

An object of the present invention is to provide a bit slice LSI,
An object of the present invention is to provide an information arithmetic device that performs an nX2 bit shifter in which the number of signal lines of an LSI is completely reduced.

[Summary of the invention]

Focusing on the least significant bit of the data that has been shifted and read out by nX2 bits, the actual shift (0°8.1'6.
24 pit shift], the pit positions read out to the least significant bits are only o,8°16.24, respectively. Further, the data read to pit position 8 are 8, 16, and 24 degrees, respectively, and the same can be considered for other pit positions.

Thus, in the case of a byte shift, for bit positions 0, 8, 16.24 being read, the input data is 0, 8, . ．． 16.24, so one LS
These bits can be input to I.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. nX
Although this is a 2-bit shift, in order to make the explanation easier to understand, an example of a byte shift (0.8° 16.24 bit shift) will be taken and explained. LSIs 301 to 304 are each one LSI, and this? 4 pieces in a row%32
Realize Bitwo. One LSI 301 has a %8-bit register 305 and a selector 30 that performs byte shifting.
Consists of 6. The input of this LSI 301 has eight signal lines 307 for convolving into the register 305.
There are eight signal lines 308 for reading at the output.

Further, a signal line 309 is used to determine which biller to be selected by the selector 306. These signal lines 307,
The pit position of 308 is 0.4°8.12,16,20
, 24.28. Bit positions 0, 8 of signal line 308
, 16. The pit positions read in 24 are 0, 16, and 24, respectively.
8, 16°24, and the signal line 308
The pit positions read out at bit positions 4, 12, and 20.28 are either 4, 12, or 20.28, respectively. The same applies to LSIs 302, 303, and 304.

Now, looking at pit position 0 of signal line 308, in the case of 0, 1, and 2.3 byte shifts, pit positions 0.8 and 16.24 of the contents of register 305 are read, respectively. Also, in signal line 308 bit position 28, %
For 0, 1, 2.3 byte shifts 1, bit positions 28, 4, 12, 20 of the contents of register 305, respectively.
is read out.

〔Effect of the invention〕

As described above, according to the present invention, the bit slice LSI
This has the effect that the number of input/output signal lines of the LSI can be reduced when all nX2 bit shifts are performed.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a byte shift, FIG. 2 is an explanatory diagram of a conventional information arithmetic device, and FIG. 3 is an explanatory diagram of an information arithmetic device of the present invention.

Claims (1)

[Claims] 1. In an information processing device that performs arbitrary n×2 bit shifting, the information processing device is divided into two or more circuit units, and each circuit unit stores bit data at pit positions spaced apart by the number of circuit units. An information arithmetic device comprising: a register for shifting the stored bit data; and a selector for shifting the stored bit data and outputting the shifted bit data to a predetermined output line.