JPS60100250A - Integrated circuit - Google Patents

Abstract

PURPOSE:To allow a device which is slow in access time to have access at optimum real time by providing a circuit which generates a prescribed time ready signal in response to an access signal from a CPU in a device to which access is made by the CPU. CONSTITUTION:An integrated circuit has a ready signal control circuit 2 built in a ROMIC1. The integrated circuit gives a lead signal and a chip select signal from a terminal 3 to a NOR circuit 4, leads out the output of said signals as data read-out control signals, inputs the signals into a NAND circuit 5 functioning as a control circuit which controls the ready signal conditions, and gives said signals to a shift register 7 through an inverter 6. Each bit output of the shift register 7 is selected by a selection circuit 9, and inputted into the NAND circuit 5 through an inverter 10. The integrated circuit changes connection of an intersecting point of the section circuit 9 and the output of the shift register 7 according to a basic clock supplied from the system, and controls the length of a ready signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit incorporating an f1 control circuit (hereinafter referred to as "■c") for data transfer.

Generally, read-only memory (hereinafter referred to as ROMJ).

) and random access memo') C, hereinafter referred to as rRAMJ. ) and other memories ■c are referred to as system memory. )K. Therefore, the interface between the memory IC and the CPU becomes a necessary problem. As for this interface problem, basically, if the addresses of the CPU and memory IC and the configuration of the data bus match, it is possible to match the interfaces. However, at this time, in response to the read signal and write signal output from the CPU, the memory IC
The problem is that the processing time (hereinafter referred to as "access time") required to read data from and write data to is not the same. The above access time is greatly influenced by the memory capacity of the memory IC, the internal circuit configuration, and the device used. In addition, in recent years, large-capacity memory is required in application systems, and memory ICs with larger capacities are being developed. - It becomes O In addition, in an application system using a battery as a power source, the memo IJ I Memory ICs with this 0MO8 configuration consume less power than memory ICs with an nMOS configuration, but have longer access times.In particular, in order to increase the degree of integration, multiple n-channel transistors are used. IL OM with 0MO8 technology connected in series,
The access time is determined by the number of transistors connected in series, so the access time is several tens of times longer than a high-speed ROM.When using a memory IC that is within the access time required by the CPU, , the CPU can operate at its original speed. However, when using a memory IC whose access time is longer than that required by the CPU, it is necessary to process read and write cycles of the CPU 1/1 to postpone read and write signals.

For this reason, a conventionally known method for prolonging read cycles and write cycles is to slow down the operating speed of C1'U so that read signals and write signals match the access time of the longest memory IC. . Also, C.P.
When a memory IC is accessed using the ready function that processes read cycles and write cycles provided in the U, the ready function is operated for a period corresponding to the access time of each memory IC. Additional circuit (
A method of providing a ready signal circuit (hereinafter referred to as a "ready signal circuit") outside the CPU is also known. However, the C of these conventional methods
The method of slowing down the operating speed of the CPU has the disadvantage that the operating speed of the CPU is slowed even when not accessing the memory IJIc, which slows down the arithmetic processing speed of the entire application system.

In addition, when using the ready function of CP[J, the above ready signal circuit is used for memory with different access times.
A separate circuit is required for each C. For this reason.

In an application system that uses many memory ICs with different access times, the ready signal circuit has the disadvantage that it is required as many times as there are types of access times of the memory ICs used in the application system.

In addition, each ready signal circuit described above has the disadvantage of complicating the circuit because a selection circuit such as an address decoder must be added to each ready signal circuit so that it operates only when the target memory IC is selected. has.

In addition, in recent years, the configuration of application systems has been miniaturized by using large-capacity memory (CPU, ROM, RA
There is also a handy type application system in which all M etc. are 0MO8. Therefore, as the application system becomes smaller, it is better to have fewer additional circuits, and adding the above-mentioned reso/f signal circuit and the above-mentioned selection circuit as in the conventional method is foolish and impedes the miniaturization of the application system. This is a major drawback as it also increases the price of the system.

The present invention improves this point by providing an additional circuit outside of C1, which allows devices with slow access times to be accessed at the optimal access time, resulting in miniaturization of the 7 stem and improved processing efficiency. An object of the present invention is to provide an integrated circuit that can perform access control signals (read signals, write signals) for data transfer from a CPU.
The present invention is characterized in that a device accessed by the CPU is provided with a circuit that generates a ready signal for a predetermined period of time in response to an access signal from the CPU.

An embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram of essential parts of an embodiment of the present invention. This example shows an example in which the ready signal control circuit 2 is built into the ROM I C1. That is, the read signal (b) input from the terminal 3 is guided to one input terminal of the NOR circuit 4. A chip select signal (a) is input to the other input terminal of the NOR circuit 4. This chip select signal +a) is a signal that becomes low level when ROMIC is selected, and when ROM1Cl is selected, lead 1g (bl becomes a ringing signal and R
Manufactured within OMIC1. The output of this NOR circuit 4 is
The signal is led out of the diagram as a data read control signal, is input to the driver circuit 5, and is also sent to the inverter. Further, the output of this NOR circuit 4 is led to an input terminal of a shift register 7.

Further, the output of the inverter is led to the reset terminal of the shift register 7. In this embodiment, the shift register 7 functions as a counter with a ``6-bit'' configuration, and is configured to shift the signal at the rising edge of the clock signal (C) inputted from the terminal 8. Each bit output of this shift register 7 is led to a selection circuit 9. The intersection 91+91+9L94t91+9 between the output of the shift register 7 and the output line of the selection circuit 9 is normally open, and each output t of the shift register 7 and the selection circuit 9
is not related to the output of Therefore, if one of the intersections of this selection circuit 9 is connected to the opposing output of the shift register 7, the output of the pick of the shift register 7 corresponding to the connected intersection will be the output of the selection circuit 9 (the inverter). (100 manpower).

In this example, since the intersection 9s is connected (marked CJ in FIG. 1), the output of the "third bit" of the shift register 7 is the output of the selection circuit 9. By changing the connection point of this selection circuit 9, the bit output of the shift register 7 can be changed. That is, the delay time can be made variable by changing the count value of the clock.

The output of the selection circuit 9 is led to another input terminal of the NAND circuit 5 via an inverter 10.

The output of this NAND circuit 5 is connected to a terminal 11, and a ready signal (j
The output source is sent to the CPU as l.

It is preferable that the intersection point of the selection circuit 9 is set at the groove bottom in the same process as the memory code setting of the ROMIC.

FIG. 2 is an operation time chart showing input signals or output signals at points indicated by x marks in FIG. 1.

With such a circuit configuration, the characteristic operation of this embodiment will be explained. When this ROM I C1 is not selected, the chip select signal (a) is at a high level, so the output of the NOR circuit 4 is at a low level, and the output of the NAND circuit 5, that is, the ready signal (j) remains at a high level. be. Here, in a system using multiple ROMICs,
C1) Ready of only the ROMIC selected by U (in order to check i), the ready signals of other ROMICs are set to high level so as not to affect the ready signal of the selected MIC.

Now, when this ROM1Cl is selected, the chip select signal t8) becomes low level. However, the read signal [
Since the shift register 7 is in a reset state while b) is at a high level, all outputs of each bit of the shift register 7 are at a low level.

Furthermore, since the output of the NOR circuit 4 is at a low level, the output of the NAND circuit 5, that is, the ready signal U) remains at a high level.

Next, when the read signal (b) changes from high level to low level, that is, when the read signal is applied from Cl-'U, the output of the NOR circuit 4 becomes high level. At this time, 10 inverters have high level signals and ready signals (
j) changes to low level. When the CPU (not shown) detects the low level of the ready signal (j), it enters a wait state to postpone memory access. Also, lead No. 13 f
b) changes to low level, the reset state of the shift register 7 is released, and when the clock signal (C) input to the terminal 8 rises (indicated by a dot in FIG. 2), the shift register 7 is activated by the NOR circuit 4. Since the high level of the output of the shift register 7 is read and shifted by 1 bit, the output of the first bit of the shift register 7 becomes a high level (indicated by ■ in FIG. 2). However, the output of the selection circuit 9 is
The output of the third bit remains at low level.

Therefore, the ready signal (jl remains at low level.When the second rise of the clock signal (C) (indicated by ■ in FIG. 2), the shift register 7 is shifted by 1 pin again. The output of the second bit of the shift register 7 becomes high level (indicated by ■ in FIG. 2), but the ready signal (j) remains at low level.

(indicated by ■ in Figure 2), the output of the third bit of the shift register 7 becomes high level (indicated by ■ in Figure 2).
), the input of the inverter IO is at high level,
The output of the inverter 10 becomes low level. For this reason,
The output of the NAND circuit 5 is at a high level, and the ready signal f
J) becomes high level (indicated by ■ in FIG. 2) and becomes active. In this state, a CPU (not shown) is notified that the data has been finalized. Therefore, if the time in which the ready signal (j) is in the inactive state (indicated by ■ in Figure 2) at the callow level is made slightly longer than the access time of JMIC, the CPU will After confirming that the level has become high, data can be input and confirmed data can be obtained from the ROMIC.

In this way, the low level (inactive state) time of the ready signal fJ) is determined by the period of the clock signal (C).
It is arbitrarily determined by the number of inputs of the clock 1r and the number tc>. Therefore, when another CPU and this ROMIC 1 are connected and a clock with a period half of the period of the clock signal (C) is manually inputted, the 96 of the selection circuit 9
After the read signal (b) becomes low level by connecting with the output of the 0-AC At-shift register 7, the clock signal (c
) O No. 6. ? The ready signal (j) is configured to be at a high level (acid dip state) at the 1i-th rising edge.

At this time, the time during which the ready 1 word (j) is at a low level (inactive state) is the same as when the intersection point 93 of the selection circuit 9 shown in the above embodiment is connected to the output of the shift register 7.

In this step, it is possible to set the inactive state of the ready signal ('') that is optimal for the access time of the ROMIC. Even if the clock period is 1.5 times, if the 98 intersection of the selection circuit 9 is connected to the output of the shift register 7, the inactive time of the ready signal tj) can be increased by +1 tons compared to the above two examples. Can be set to similar values.

In this way, by changing the connection between the intersection of the selection circuit 9 and the output of the shift register 7 according to the reference input clock supplied from the system, the length of the ready signal can be adjusted according to the access time of the device to be accessed. can be controlled. Furthermore, the history of the selection cycle TNr9 is designed so that it can be changed in the same process as the ROMIC memory code, so that when setting the ROMIC memory code,
The setting of the selection circuit 9 can be set to the optimum number of clocks depending on the reference input clock of the CPU or the system.

In addition, in the above example, a weak implication was shown in which the number of cyclic signal inputs can be programmed by using a shift register to move the connection point 1r of the selection circuit. This can also be realized by a frequency dividing circuit connected to the . It can also be realized by using a counter in place of this shift register and counting the number of manually inputted clock signals according to the time to be delayed. In this case, it is preferable to have a circuit configuration that includes a mode register, sets a predetermined count number, and controls the ready signal when the count number and the contents of the mode register match.

The beam of the present invention, Ju l-induced φ light 1- odd 1 et al V-J oil λ
* A circuit is provided on the same chip as the integrated circuit to be accessed, which counts the access time, counts the access time in the accessed IC, and controls the ready signal accordingly. Additionally, a device with a slow access time can be accessed at the optimum access time for the CPU without providing an external additional circuit.

Furthermore, the system can be made smaller and the processing efficiency of the system can be improved. Furthermore, when setting the memory code of the ROMIC, the selection circuit can also be set, so the number of clocks can be changed depending on the frequency of the input clock supplied from the system and CPU. This has advantages such as being able to generate a ready signal with a long access time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a narrow section according to an embodiment of the present invention. FIG. 2 is an operation time chart showing the input signals or output signals at the points indicated by the X marks in the wJ1 diagram. 1...ROMIC, 2...Ready (i
No. control circuit, 3, 8...terminal, 4...tour circuit, 5...Nand circuit, 6.10...
...Inverter, 7...Shift register, 9.
...Selection circuit.

Claims (1)

[Claims] (1) Integrated circuit KL that transfers data with the CPU
- an integrated circuit having an internal circuit that receives an access request signal from the CPU and generates an I/H signal for instructing the CPU that data is uncertain for a predetermined period in response to the access request signal; .