JPS5999772A - Manufacturing method of thin film transistor - Google Patents
Manufacturing method of thin film transistorInfo
- Publication number
- JPS5999772A JPS5999772A JP57208991A JP20899182A JPS5999772A JP S5999772 A JPS5999772 A JP S5999772A JP 57208991 A JP57208991 A JP 57208991A JP 20899182 A JP20899182 A JP 20899182A JP S5999772 A JPS5999772 A JP S5999772A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- manufacturing
- polycrystalline silicon
- film
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
- H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
Landscapes
- Thin Film Transistor (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明はシリコン薄膜例えば多結晶シリコンやアモルフ
ァスシリコンを用い７ｃＭＯ８型の薄膜トランジスタ（
以下ＴＰＴと略丁）に於いて、特性の同上を図つプζ製
造方法に関する。Detailed Description of the Invention The present invention uses a silicon thin film such as polycrystalline silicon or amorphous silicon to produce a 7cMO8 type thin film transistor (
Hereinafter referred to as TPT, the present invention relates to a manufacturing method for achieving the same characteristics as those described above.
シリコン薄膜を用いたＴＰＴに於いてＨｌＴＰＴがＯＦ
Ｆ林態の時に流れるリーク電流を低減させる方法とし
て、前記シリコン薄膜の膜厚を小さくてればする程良い
ことがわ７１”っている。し７＞しながら、シリコン薄
膜の膜厚を小さくしていくと、薄膜に形成されるソース
、ドレイン拡散層と、配線用金属と・のオーミックなコ
ンタクトがとれにくくなるという問題が生ずる。この解
決策としでに例えば、チャンネルの形成される領域の膜
厚を、ソース、ドレインの形成される領域のｍ厚エリも
小さくすればよ、す。In TPT using silicon thin film, HlTPT is OF
As a method of reducing the leakage current that flows during the F state, it is known that the thinner the silicon thin film is, the better. As a result, a problem arises in that it becomes difficult to make ohmic contact between the source and drain diffusion layers formed in the thin film and the wiring metal. The film thickness can be reduced by reducing the m thickness area of the region where the source and drain are formed.
本発明に上述した構造を有するＴＦ、Ｔの製造方法に関
するものである。以下、図面に従って説明する。The present invention relates to a method for manufacturing TF and T having the above-described structure. The explanation will be given below according to the drawings.
第１図μ従来の多結晶シリコ、ンを用い７ｃＴＦＴの製
造方法である。同図（ａ）で、絶縁基板ＩＱ１に多結晶
シリコン１０２を所定のパターンに加工しゲート酸化膜
１０３を形成する。次にＮ型の不純ｖＩＪを有する多結
晶シリコン１０４をゲート電極として形成した後、イオ
ン注入法にエリＮ型の不純物１０５を注入し、ソース、
ドレイン拡散層１０６を形成し１このが同図（ｂ）であ
る。層間絶縁膜１０７゛を全曲に形成した後、コンタク
トホールの窓開けを行ったのが同図（Ｃ）である。最侯
にＭ等の１記線用金）Ｋ １０８ ｆ配線形したものが
同図（ｄ）である。こうして試作されたＴＰＴ特性に於
いて、ｌ−ランジスタがＯＦＦ状態に流扛るリーク電流
は、多結晶シリコン１０２の膜厚を小さくしてゆけば、
低減することができる。しかし、多結晶シリコンの膜厚
を小さくしてゆくと、配勝用金属として例えばｆｉＪｌ
、 Ａｆ、−Ｓｉを用いた場合、拡散層を突き抜けて
オーミック々コンタクトを得ることが内錐になる。Figure 1 shows a method of manufacturing a 7c TFT using conventional polycrystalline silicon. In FIG. 3A, a gate oxide film 103 is formed on an insulating substrate IQ1 by processing polycrystalline silicon 102 into a predetermined pattern. Next, after forming polycrystalline silicon 104 having an N-type impurity vIJ as a gate electrode, an N-type impurity 105 is implanted using an ion implantation method, and the source and
A drain diffusion layer 106 is formed as shown in FIG. 1(b). After forming the interlayer insulating film 107' on the entire surface, contact holes were opened, as shown in FIG. 3(C). The figure (d) shows a wiring type with K 108 f wiring for M, etc. at the top. In the TPT characteristics prototyped in this way, the leakage current that flows when the l-transistor is in the OFF state can be reduced by decreasing the thickness of the polycrystalline silicon 102.
can be reduced. However, as the film thickness of polycrystalline silicon is reduced, for example, fiJl can be used as a winning metal.
, Af, -Si, the inner cone penetrates through the diffusion layer to obtain ohmic contact.
従って、エリリーク電流を低減略せる可能性を持チナが
ら、多結晶シリコンの膜厚（り、コンタクトがとれるか
どう刀１によって決定さｔ’してし−まつ。不発明は以
上の欠点を改嵜し１こＴＦＴの構造に関し本発明の目的
とするところに、チャンネルの形成される領域の多結晶
ソリコンの膜厚のみケ小さくすることＶこよってリーク
電流を低減すると共に、ソース、ドレイン拡散層と配線
用金属とのオー７ツクなコンタクトが得られる構造を有
するＴＦＴの製造方法を提供することにある。以下、第
２図に従って本発明の一実施例を説明する。Therefore, while there is a possibility of reducing the leakage current, it is determined by the thickness of the polycrystalline silicon film and whether or not contact can be made. Regarding the structure of a TFT, it is an object of the present invention to reduce only the thickness of the polycrystalline silicon in the region where the channel is formed, thereby reducing leakage current, and reducing the thickness of the source and drain diffusion layers. It is an object of the present invention to provide a method for manufacturing a TFT having a structure in which an open contact can be made between the metal and the wiring metal.Hereinafter, an embodiment of the present invention will be described with reference to FIG.
第２図（ａ）で、絶縁基板２０１上に多結晶シリコン２
０２ｆ所定のパターンに形成加工する。次に全面にシリ
コン窒化膜２０３ｉ形成した後、チャンイ、ル慎域のみ
のシリコン窒化膜全除去したのが同図（ｂ）である。そ
の後同図（Ｃ）のようにチャンネル領域のみ選択酸化全
行い酸化膜２０４全形成する。In FIG. 2(a), polycrystalline silicon 2 is placed on an insulating substrate 201.
02f Forming into a predetermined pattern. Next, after forming a silicon nitride film 203i on the entire surface, the silicon nitride film was completely removed only in the opening and closing areas, as shown in FIG. 2(b). Thereafter, as shown in FIG. 3C, only the channel region is selectively oxidized and the entire oxide film 204 is formed.
この時チャンネル領域の多結晶シリコンが所定の膜厚に
なる址で選択酸化を行う。次に、シリコン窒化膜２０６
及び酸化膜２０４を除去した後、ゲート酸化膜２０５全
形成したのが同図（ｄ）である。At this time, selective oxidation is performed until the polycrystalline silicon in the channel region reaches a predetermined thickness. Next, the silicon nitride film 206
After removing the oxide film 204, the gate oxide film 205 is completely formed, as shown in FIG.
その仮、Ｎ型の不純物を有する多結晶シリコンを全曲に
デポし、ゲート電極２０６ｆ：形成加工する。Temporarily, polycrystalline silicon containing N-type impurities is deposited on all the tracks, and a gate electrode 206f is formed and processed.
］−〃）る段、イオン注入法Ｖ？ＣＬ’）Ｎ型の不純物
全注入し、ソース、ドレイン拡散層２０７’ｉ形成した
のが同図（ｅ）である。その後、層間絶縁膜２０８を全
面（で形成し、コンタクトホールの窓開は全行いＭ等の
配線用金属全配線形成したものが同図（ｆ）である。上
述した製造方法によれば、選択酸化に工９形成される酸
化膜厚全制御することＶｒＣ工っ、トランジスタのリー
ク電流全低減させることができると共に、ソース、ドレ
イン拡散層の形成される多結晶シリコンは、オーミンク
なコンタクトヲトるに十分な膜厚である。]-〃)ru stage, ion implantation method V? CL') N-type impurities are fully implanted to form source and drain diffusion layers 207'i, as shown in FIG. After that, the interlayer insulating film 208 is formed on the entire surface, all contact holes are opened, and all metal wiring for wiring such as M is formed as shown in FIG. By fully controlling the thickness of the oxide film formed during oxidation, the VrC process can completely reduce the leakage current of the transistor, and the polycrystalline silicon on which the source and drain diffusion layers are formed can be used to form ohmic contacts. The film thickness is sufficient.
以上のように、本発明ｌ−］：秀性の同上全図ったＴＰ
Ｔの製造方法である。As described above, the present invention l-]: A TP that has all the features of the same as above.
This is a method for manufacturing T.
なお本実施例で汀、薄膜として多結晶シリコンを用いた
がアモルファスシリコン等・池のシリコン薄膜にも応用
できる。丑た、本発明ではＮチャンネルのＴＦＴｉ例【
て挙げたが、もちろんＰチャンネルのＴＰＴにも応用で
きる。Although polycrystalline silicon was used as the base and thin film in this embodiment, it can also be applied to amorphous silicon or other similar silicon thin films. However, in the present invention, an N-channel TFTi example [
Of course, it can also be applied to P-channel TPT.
である。It is.
２０１・・・絶縁基板 ２０２・・・多結晶シリコン ２０３・・・シリコン窒化膜 ２０４ 選択酸化膜 ２０５・・・ゲート酸化膜 ２０６・・・ゲート電極 ２０７・−・ソース、ドレイン拡散層 ２０８・・・層間絶縁膜 ２０９・・配線用金属 以 上 出願人 株式会社諏訪梢工舎 代理人 弁理士最上 務 ｚｏｌ −３７７− 鉋２目201...Insulating substrate 202...polycrystalline silicon 203...Silicon nitride film 204 Selective oxide film 205...Gate oxide film 206...gate electrode 207 -- Source, drain diffusion layer 208...Interlayer insulation film 209...Metal for wiring that's all Applicant: Suwa Kozue Kosha Co., Ltd. Agent: Patent Attorney Mogami zol -377- 2nd plane
Claims (1)
択的に酸化する工程と、形成された酸化ｗＡヲ除去し、
ゲート酸化膜を形成する工程と、前記酸化膜の除去され
た凹部にゲート電極を形成する工程とを有することを特
徴とする薄膜トランジスタの製造方法。 （２） シリコン薄膜として多結晶シリコンを用いた
ことを特徴とする特許請求範囲第１項記載の薄膜トラン
ジスタの製造方法。[Claims] (In the 11-7'Jcon thin film, a step of selectively oxidizing the channel region and removing the formed oxide wA,
A method for manufacturing a thin film transistor, comprising the steps of forming a gate oxide film and forming a gate electrode in a recessed portion from which the oxide film has been removed. (2) A method for manufacturing a thin film transistor according to claim 1, characterized in that polycrystalline silicon is used as the silicon thin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57208991A JPS5999772A (en) | 1982-11-29 | 1982-11-29 | Manufacturing method of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57208991A JPS5999772A (en) | 1982-11-29 | 1982-11-29 | Manufacturing method of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5999772A true JPS5999772A (en) | 1984-06-08 |
Family
ID=16565511
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57208991A Pending JPS5999772A (en) | 1982-11-29 | 1982-11-29 | Manufacturing method of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5999772A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63262875A (en) * | 1987-04-20 | 1988-10-31 | Nec Corp | Manufacture of thin-film transistor |
| JPH0199261A (en) * | 1987-10-12 | 1989-04-18 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH02185068A (en) * | 1989-01-12 | 1990-07-19 | Toshiba Corp | Manufacture of field-effect transistor |
| EP0635880A1 (en) * | 1993-07-22 | 1995-01-25 | Commissariat A L'energie Atomique | Method of manufacturing a transistor using silicon on insulator technology |
| US5792678A (en) * | 1996-05-02 | 1998-08-11 | Motorola, Inc. | Method for fabricating a semiconductor on insulator device |
| DE10233663A1 (en) * | 2002-07-24 | 2004-02-19 | Infineon Technologies Ag | Production of a SOI substrate comprises preparing a SOI substrate by embedding a trenched oxide layer between a crystalline silicon layer and a silicon substrate |
| DE10250840A1 (en) * | 2002-10-31 | 2004-05-19 | Infineon Technologies Ag | Single-crystal silicon-on-insulator field effect transistor production, includes ion implantation to produce localized defects, and tempering to form oxide clusters |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5891678A (en) * | 1981-11-27 | 1983-05-31 | Nec Corp | Semiconductor device and its manufacture |
-
1982
- 1982-11-29 JP JP57208991A patent/JPS5999772A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5891678A (en) * | 1981-11-27 | 1983-05-31 | Nec Corp | Semiconductor device and its manufacture |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63262875A (en) * | 1987-04-20 | 1988-10-31 | Nec Corp | Manufacture of thin-film transistor |
| JPH0563013B2 (en) * | 1987-04-20 | 1993-09-09 | Nippon Electric Co | |
| JPH0199261A (en) * | 1987-10-12 | 1989-04-18 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH02185068A (en) * | 1989-01-12 | 1990-07-19 | Toshiba Corp | Manufacture of field-effect transistor |
| EP0635880A1 (en) * | 1993-07-22 | 1995-01-25 | Commissariat A L'energie Atomique | Method of manufacturing a transistor using silicon on insulator technology |
| FR2708142A1 (en) * | 1993-07-22 | 1995-01-27 | Commissariat Energie Atomique | Method of manufacturing a transistor in silicon on insulator technology. |
| US5439836A (en) * | 1993-07-22 | 1995-08-08 | Commissariat A L'energie Atomique | Method for producing a silicon technology transistor on a nonconductor |
| US5792678A (en) * | 1996-05-02 | 1998-08-11 | Motorola, Inc. | Method for fabricating a semiconductor on insulator device |
| DE10233663A1 (en) * | 2002-07-24 | 2004-02-19 | Infineon Technologies Ag | Production of a SOI substrate comprises preparing a SOI substrate by embedding a trenched oxide layer between a crystalline silicon layer and a silicon substrate |
| DE10250840A1 (en) * | 2002-10-31 | 2004-05-19 | Infineon Technologies Ag | Single-crystal silicon-on-insulator field effect transistor production, includes ion implantation to produce localized defects, and tempering to form oxide clusters |
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