JPS5991558A - Method for testing program - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a data processing device that includes at least a processor and a read/write storage device that stores all programs that run on the processor. 7 Concerning a program test method that makes it possible to generate breakpoint interrupts without increasing the memory capacity of the device (b) Prior art and problems In the prior art, when a breakpoint is specified, it is stored at the specified address. Replace the instruction (Ib) with the instruction (dW), start the entire -J: line of the instruction from the specified point, and as a result of executing the previously replaced instruction (SWI) i, When an interrupt occurs and the interrupt is recognized, the address replaced first is sw.The disadvantage is that it requires an area to store the entire address and the replaced instruction. .

FIG. 1 is a diagram showing a memory map in the conventional method.

In the figure, C is an area where normal operation programs are stored, and a
is an area where the test program is stored, b is an area where all addresses and instructions to be replaced are stored, and mXn is a breakpoint address, LDA.

LDB is an instruction that has been replaced. In this way, in the conventional method, 541 diagrammatic areas are required, which increases the overall memory capacity, or increases the ability to specify breakpoint 2, /i-(memorizes the address and addition to be replaced). However, there was a drawback in that it had to be limited by the area in which it would be used.

(・9 Purpose of the Invention The purpose of the present invention is to eliminate the need for an area outside the program area under test to store addresses and instructions where breakpoints are specified, and to provide all program testing means equivalent to the conventional method. It is in.

B) Structure of the Invention In order to achieve the above object, the present invention provides a data processing device that includes at least a processor and a readable/writable storage device that stores all the programs that run on the processor. mode indicating means for adding a parity pit of at least l bits to the device, and for holding information that is accessible by the processor and instructs whether the data processing device is in an operational mode or a test mode; parity inversion instruction means that holds information instructing the inversion of parity pits that are accessible and to be written to the storage device; and a parity that is controlled by the parity inversion instruction means and generates a parity pit to be written to the storage device. generating means; parity checking means for checking all parity pits read from the storage device; breakpoint interrupt instruction means for creating and retaining information indicating that the data processing device is in a breakpoint interrupt state; The present invention is characterized in that by inverting the parity pit, all breakpoint interrupts are generated at the address position of the instruction under test.

Keya Embodiment of the Invention FIG. 2 is a diagram showing a memory map in the embodiment, and FIG. 3 is a block diagram of a data processing apparatus in the embodiment according to the present invention. In FIG. 3, 3 is a microgrocer MPU1 commercially available under the name M O6800, etc.
There are terminals such as address iAo- and Arthas DO-'7. J indicates a group of external registers for applying the present invention;
, 1-2 can write the 1i7 information supplied from the MPU 3. 1-1 shows a flip-flop that switches between operational mode and test mode, Noritsubu flop 1-2
is the parity code to be written in the parity focus section 2-1 of the memory, and the parity generation that all the codes are generated, and the AND of ♀2-3.
Connected via gate knee 5 and parity generator 2-3
7 shows a 7-linopflop that completely inverts the polarity of the signal generated from the circuit. AND gate 1-6.1-7 connects Q1 of flip-flop j,-1 and memories 2-2 and 2.
Read test signal 2-10 from the information read from -1
(1-3.1-4 are connected to the parity check circuit 2-4 which generates 5.1-3.1-4 are flip 70 which are used to hold all state information indicating breakpoint interrupts and memory failures, respectively.
7, Norinob flop 1-4 (7) Qka”
1'(7), the signal -q 2-10 y): When it becomes 1#, the flip-flops 1-3 become 1", and when the flip-flops 1-1 are both "y", the signal 2-10 is J
'', the output of the gate 1-5 is set to 1.
In this case, when the address tone in the parity bit part 2-1 t7c4 is read, the 5 bits which become "1" are also connected to the interrupt input terminal NM1 of the iJPU 3. 2-8 is also connected to the interrupt input terminal NM1 of the iJPU 3. 2 to 1 is the information path line, 2-9 is read from the memory, 1 information is read, and from the MPU 3 via the path amplifier 2-6, 2-7, including the external register, easy to read clue. The grooves are designed to be effective.

In the operation mode, the MPU 3 outputs an evening signal that sets the Qt'O'' of the clip-flop 1-1.

This will prevent errors from being detected when reading the memory.7'
l-4f″1#. This ensures system reliability.

In the trial 1 thrift mode, the Q of the clip flop 1-1 is set to PAL# by a known method.
- Output the 1H report that changes the gold to 1" from the MPU 3.K. - Read all lines for addresses m and n shown in Figure 42, respectively, and output the same information from the iMPU 3. , the output of the parity generator 2-3 (P in FIG. 2) is written into the parity bit section 2-1.
)t-Write it down.

This program is executed by a test program stored in the area shown in FIG. 2A. In this state, when the MPU 3 reads the memory from address m or n in order to execute the instruction at address m or n in the program area under test C, the parity check circuit 2-4 causes the output line 2-10 to
This causes an interrupt to occur, and since the Q of Noritsubu flop l-1 is 'l' and Q is 0#, only Noritsubu flops 1-3 become '1#.'As a result, ,
By reading the Noritub flops l-3 and 1-4, the test program can know that Ik is a breakpoint interrupt rather than a memory failure.

Since the instruction code written at address m or n of the program under test has not been rewritten, the instruction is
Even if it is executed in 03, it does not mean that the program under test is completely destroyed, and the instructions replaced by the conventional method are restored.
The extra area (b in FIG. 1) for execution is also no longer necessary. Also, since b is not required, there is no limit to the number of breakpoints specified.

(f) Effects of the Invention According to the present invention, the area bV′i in FIG. can be extended to 5 top steps in the program under test. Furthermore, although not shown in the example, in order to cancel a breakpoint that has already been specified, it is sufficient to read the corresponding address, set all flip-flops 1-2 to 0#, rewrite and execute the entire test program. itself can be simplified.

[Brief explanation of the drawing]

Figure 1 shows the memory map in the conventional method, Figure 2 shows the memory map in the conventional method.
This figure shows a memory map in an embodiment, and FIG. 3 is a block diagram of a data processing device in an embodiment according to the present invention. In FIG. 3, 1-1 to 1-4 are clip flops;
2-1 is the parity bit part of the memory, 2-2 is the memory IJ
, 2-3 is a parity generator, 2-4 is a hardware circuit, and 3 is a microprocessor.

Claims (1)

[Claims] In a data processing device including at least a processor and a read/write storage device for storing all programs running on the processor, at least one bit of parity pit is attached to the storage device, and the processor +!, which can be accessed by +! and indicates whether the data processing device is in operational mode or test mode. mode instruction means for holding @'c;
parity inversion instruction means that is accessible by the processor and holds information that instructs the inversion of parity bits to be written to the storage device; parity generation means for generating parity; parity check means for checking parity bits successively output from the storage device; A breakpoint interrupt instruction means for creating and holding information indicating that the processing unit is in a breakpoint interrupt state is provided, and when the processing unit is in a test mode state, a parity bit at the address position of the instruction under test on the storage device is provided. A program testing method characterized in that a breakpoint interrupt is generated at the address position of the instruction under test by inverting the instruction.