JPS5989034A - Input circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to an input circuit suitable for an ItL circuit.

[Prior art]

1”L (Integrated In, 7tction
The Logic) circuit is realized by using a lateral PNP transistor made using normal bipolar semiconductor manufacturing technology as a current load element, and by operating NpN transistors with a common collector region in the opposite direction (that is, the emitter region is common). This is a logic circuit. Therefore, a normal bipolar Ic circuit and a 12L circuit can be
Various applied ICs are being manufactured that are incorporated on C chips and combine the analog functions of bipolar elements and the digital functions of I2L.

However, I! The operating input voltage of the L circuit is as low as about 1 V, and when it is coupled to an analog circuit, it is common to use an input circuit as an interface. Therefore, conventionally, an input circuit consisting of an analog circuit as shown in FIG. 1 has been used. In the figure, 1 is an I2L circuit provided with an I''L basic element consisting of a PNP transistor 9 for the injector, and inverse IV pN transistors 8 and 10 for driving. 2 is a NpN transistor 3, 4.
PNP) This is an analog input circuit consisting of transistors 5, 6, resistor 7, etc. In such a configuration, when the input signal VIpt is applied to the differential amplifier consisting of transistors 3 and 4 of the analog input circuit 2, the transistor 3 turns OFF, the transistor 4 turns ON, and the transistor 4 turns OFF.
PNP (where the current flowing through is diode-connected)
It also flows to transistor 5. Furthermore, the base is connected to P
NP) Due to the current mirror action, Ranjistaro also has
A current of approximately the same value as the current flowing through the transistor 5 flows, becomes the base current of the I-retransistor 8, turns on the transistor 8, and transmits the "ON" signal to the I"L circuit. On the other hand, the input signal Vrpt When the polarity is reversed, transistor 3 turns on and transistor 4 turns off, making the PNP
) The transistors 5 and 6 are also turned off, and the I'L circuit is turned off.
However, since the base region of a pNP transistor is generally long and it takes time for the injected minority carriers to disappear, the switching speed from 'ON' to 'OFF' is slow. Therefore, even in the configuration shown in FIG. 1, the speed at which the input signal Vty is transmitted to the inverse transistor 8 of the I2L circuit 1 is slowed down by the switching speed of the pNP)9 transistor 6 from "ON@ to @OFF".

In addition, in the conventional input circuit, the charge in the capacitance between the base and emitter of the I"L reverse transistor 8 at the time of "OIV" is discharged through the resistor 7 when it is "OFF". ” has the disadvantage that the switching speed is even slower.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an input circuit that combines an analog circuit and an I''L circuit at high speed, eliminating the drawbacks of the prior art described above.

[Summary of the invention]

The features of the present invention are that PNP (PNP) transistors with slow switching speed are differentially operated as input circuits, and 12
By providing a transistor that extracts the charge from the base-emitter capacitance of the L reverse transistor (<IVPN), 1! This is because the transmission speed to the L circuit has been increased.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. Second
In the figure, 11.12 is a PNP that constitutes a differential amplifier.
) transistor, 13.14 is NPN) transistor 11 current flows into transistor 1 by current mirror action. The collector of transistor 14 is connected to the collector of transistor 12σ) and further connected to the base of inverse transistor 80 of the I''L circuit.

In the above configuration, when the signal Vzx is input at ℃, transistor 11 is turned off and t2 is turned on, the diode-connected transistor 13 is also turned off, the transistor 14 is also turned off, and the entire current of the transistor 12 is
The base current of transistor 8 of the ItL circuit becomes “O
On the other hand, when a signal Vrpt of opposite polarity is input and transistor 11 is turned on and transistor 12 is turned off, the current of transistor 11 flows to transistor 13, and a current approximately equal to the value flows to transistor 14. As a result, P7vP
) The current in transistor 12 does not completely turn off, but flows a little, becoming the transistor 80 pace current, and even though the signal is OFF, even if you try to keep transistor 8 in the ON state, the above PIVP ) current in transistor 12 is forced. to the transistor 14, the transistor 8
0 pace current disappears, transistor 8 immediately turns OFF
F, and the °OFF' signal can be transmitted at high speed. Furthermore, the charge in the base-emitter capacitance of the ItL reverse transistor 8 is also sucked into the transistor 14 by a similar current mirror effect, so that the transistor 8 is turned off at high speed.
It will be FF.

As described above, according to the present invention, the current of the differential KPIVP transistor is turned on and off depending on the input signal.
'f: f) When 1 is ON, it is direct -1t-K, when 0FIP, it is due to the current mirror action of the 1vPN transistor,
By flowing it to the base of the inverse NPN transistor of the I''1 circuit, the input signal .

FIG. 6 shows another embodiment of the invention, in which the same elements as in FIG. 2 are given the same reference numerals. In this embodiment, the NPN transistors 13 and 14 constituting the current mirror shown in FIG.
．． It is composed of 16 parts. It is obvious that this embodiment also has the same high-speed switching effect as the embodiment shown in FIG. 2. Furthermore, in this embodiment, the transistor 15
Since ゜16 is composed of an inverted NPN transistor with an I''1 circuit, it is possible to create a structure based on a conductor structure in which the inverse transistor 8 and the emitter region (collector region of the forward transistor) are common. , high integration of semiconductors is also possible.

FIG. 4 shows still another embodiment of the present invention, in which the same elements as in FIG. 3 are given the same reference numerals. In this embodiment, the inverse NpN)-y transistor 15 and Is of the I"1 circuit configured as a current mirror shown in FIG. 3 are constructed with a multi-collector inverse AI/)A+) transistor 17 of the ILL circuit. One collector of 17 is connected to the base, and the other collector is connected to the base of the inverse transistor 8 of the next stage 12L circuit and the PNP of the analog circuit.
) is connected to the collector of transistor 12. In this embodiment as well, the current flowing through the transistor 11 flows to the collector connected to the base of the transistor 170, and the multi-collector action causes the same current to flow through the other collectors.

In other words, a current mirror effect occurs. As a result, it is clear that this embodiment also has the same high-speed switching effect as in FIGS. 2 and 3.

In addition, since the current mirror circuit composed of two NpN) run rasters can be composed of one multi-collector transistor of the I circuit, there is an advantage that the semiconductor can be more highly integrated.

FIG. 5 shows another embodiment of the invention, in which the same elements as in FIG. 2 are given the same reference numerals. Fifth
In the figure, 26.27 is a bias voltage power supply, 20.
21 is a constant current operation PIVP) transistor, 22.2
3 is a current mirror N for the current of transistors 20 and 21.
pN) PNP flowing to transistors 13 and 14) The base is grounded with the transistor. Reference numerals 18 and 19 designate differential pair NpN transistors that operate in response to the input signal Vxpt, and sink the currents of the transistors 20 and 21, respectively. 24 and 25 are transistors 1; 118 and 19 saturation prevention diodes.

In the above configuration, when the input signal VIN is applied and transistor 18 is turned on and transistor 19 is turned off, all of the current in transistor 20 flows to transistor 18, transistor 22 is turned off, and transistors 13 and 14 are also turned off.
becomes. On the other hand, the current of transistor 21 is
9 is OFF, the current flows through the transistor 23 and turns on the transistor 8 of the I"1 circuit. Also, when the opposite polarity of the input signal Vzy is input, the transistor 18 turns OFF,
H' is turned on and becomes 1, and contrary to the above, transistor 14
turns on, turning off transistor 8 of the 111 circuit. In this way, in this embodiment as well, the PNP transistor 22 turns off UIV and OFF differentially according to the input signal.
．． The ON and OFF signals can be transmitted to the I"1 circuit at high speed via the PNP
) Since the transistors 22 and 23 are used in a grounded base configuration, they also have the advantage of being able to operate at higher speeds compared to the grounded emitter configuration of the transistors 11 and 12 in the embodiment shown in FIG.

Also, the current mirror mmNPN transistors 13, 14 of the embodiment of FIG. 5 are replaced by the transistors 15, 14 of the embodiment of FIG.
It is obvious that similar effects can be obtained using the transistors 16 and 17 of the embodiment shown in FIG.

〔Effect of the invention〕

As explained above, according to the present invention, the transmission speed is high;
It is possible to provide a 12L input circuit that allows for high integration of semiconductors.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional input circuit, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a block diagram of another embodiment of the present invention, and Fig. 4 is a block diagram of a further embodiment of the present invention. FIG. 5 is a block diagram of another embodiment of the present invention. 3.4. t3, 14.18.19 ・・・・・・-41・
・NPN) transistor 5.6, 11, 12, 20, 2
1, 22, 2g...7) #, /) ) transistor 8.
15.16...Song/Tap...---Tap/
・・・・・・Reverse NPN transistor 17・・Song・・・・・・・・・・・・・・・・・・・・・・
...Open--Song...Multi-collector reverse NpN
) 41 diagrams of transistors! Fang 2

Claims (1)

[Claims] 1. A first device that performs differential KON-OFF according to an input signal.
0PIVP) The transistor and the second PNP) The transistor and the pace collector are connected, and their connection point is the first pnp.) The transistor and the pace collector are connected to the first NpN.) The transistor and the pace collector are connected to the first NpN.
N) a second NPN transistor connected to the pace collector connection point of the transistor, the collector of which is connected to the collector of the 20th PIVP transistor;
An input circuit characterized in that it is connected to the pace of an NPN) transistor for driving an ItL circuit. 2. The first NPN) transistor and the second ONPN
2. The input circuit according to claim 1, wherein the transistor is constituted by an inverse NpN transistor of an ItL circuit. 3. The first NpN) transistor and the second ONPN
ItL circuit multi-collector inverse 7vPN transistor
2. The input circuit according to claim 1, wherein the input circuit is composed of transistors.