JPS5988869A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an MOS transistor of extremely high mobility by providing a gate electrode on lead chalcogenide crystals having a plane (111) via a gate insulation film. CONSTITUTION:The lead chalcogenide crystals of large holes and mobility are used as the substrate of the MOS transistor. In other words, a (111) wafer 11 is cut from a P type PbTe single crystal, and the carrier concentration is set at -10<15>/cm<3> by high temperature heat treatment wherein Te vapor pressure is controlled. Next, BaF2 is vapor-deposited after polishing the surface satisfactorily into the gate insulation film 12, and a Pb gate electrode 13 is provided thereon. Thereafter, with the electrode 13 as a mask, N<+> type source regions 141 and 142 are formed in the substrate 11 on both side thereof by Bi ion implantation. Thus, the N-channel MOS transistor whose field effect mobility at liquid He temperature is approx. 500,000cm<2>/V sec is obtained. An N-channel is described here, but a complementary type of a P-N channel may be also available.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which an insulating dart field effect transistor is formed using lead chalcodanide crystal.

[Technical background of the invention and its problems]

The operating speed of a semiconductor device or integrated circuit is determined by the mobility of electrons or holes flowing through the device.

Conventionally, GaAs, AZ, G a , ++ XA s have been used as semiconductor devices with higher mobility than silicon devices.
etc. using compound semiconductor materials that have an electron mobility of 8000 cells/v-see at room temperature, or using these materials and applying new impurity addition methods such as modulation doping to improve electron transfer at low temperatures. Direct the degree
Things that can cause a fire are being considered. But I'm scared, Rano■
In group 1V compound semiconductor materials, the electron mobility is several 10
0 0cJ/v-see ~1 0 0,0 0 07
It stops at /y-see.

On the other hand, complementary circuits are widely used in semiconductor integrated circuits due to their large noise margin, low power consumption, and low power consumption of 2g%. is constrained by the lower value of mobility. - In the ■-■ group compound semiconductors mentioned above, although the electron mobility is high as described in 1], the hole mobility is low at about one-tenth of the current electron mobility, so complementary circuits are required. When configured, high electron mobility does not directly lead to improved performance.

In order to solve these difficulties, the present inventors proposed a complementary circuit using a lead chalcogenide crystal.

Lead chalcodenides include PbS, Pb5e and PbTe
It is said that the conduction band and valence band have extremely similar electronic structures.

Therefore, the movements e of electrons and holes are approximately equal, and by cooling to the liquid helium temperature, both values become several 10,
000 cfl/v-8ec -100,000 cfl
/v-sec. As described above, since lead chalcodanide exhibits similar high mobility for both electrons and holes, a high performance circuit can be obtained by forming a complementary circuit.

However, according to detailed experiments conducted by non-inventors,
The following problems were found.

In junction field-effect Sung transistors using lead chalconide crystals and complementary circuits using polar transistors, predictions can be made based on carrier mobility and lifetime data obtained from measurements of semiconductor materials before device formation. Although the switching speed, etc.
- In the case of lannostars (hereinafter referred to as MOS transistors), such a correlation could not always be found. This is because junction field effect transistors and bipolar transistors use carrier transport inside the crystal, whereas M
This is thought to be due to the difference in the operating mechanism in which the OS l-rank star utilizes gear travel on the crystal surface.

[Purpose of the invention]

Invention No. 117J: An attempt is made to provide a semiconductor device t# in which high mobility IW is expressed in a MOS Lan-Zostar circuit using a lead chalcoke 9nide crystal with high electron and hole mobility. It is something to do.

[Summary of the invention]

The present invention is characterized in that a (1st) plane is used as a lead chalcogenide crystal, and a MOS run-zoster is constructed in which a dirt electrode is formed on this (Ill) plane via a gate insulating film.

In this case, the crystal used may be a bulk single crystal,
For example, MB on an insulating substrate such as B a F2, CaF2, etc.
Heteroepitaxial growth was carried out using the K method etc. (1.
11) It may be a thin film single crystal. Or also,
An insulating film is deposited on a lead chalcogenide crystal substrate, an opening is made in a part of the insulating film, an amorphous lead chalcogenide thin film is deposited, and an energy beam is scanned and irradiated onto the film to cause crystallization through the opening. A single-crystal thin film obtained by

〔Effect of the invention〕

By using the (111) plane as the lead chalcodenide crystal surface for both n-channel and p-channel MO8) transistors, the electron and hole mobilities are higher than when other planes are used. That is, for both n-channel and p-channel MOS transistors, (1, (10)
However, the moving I tail is about 50% thicker than that of the well-formed one. Therefore, it can be said that the large carrier mobility effect of lead chalcodanide at low temperatures can be maximized. By using such high-mobility MOS transistors, the circuit can operate at high speed. In particular, since the maximum mobility is achieved when both n-channel and p-channel MOS transistors are formed on the (til) plane, the operating speed of a complementary circuit constructed by providing both transistors on the same chip is maximized. can do.

[Embodiments of the Invention] As shown in FIG.
) The 11 gold wafer was cut out, and after setting the carrier yarn/4 degree to p~10/- by high temperature heat treatment with Te vapor pressure controlled, the surface was well polished and B a F2
A dirt insulating film 12 was formed by evaporation of PB, a gate electrode 13 was formed by evaporation of PB, and an n layer 141.14□ which became the source and drain was formed by Bl ion implantation to form an N6 one-channel MO8) transistor. . The field effect mobility μFF at liquid He temperature is 500,000 crL/v
It was sec. On the other hand, in the n-channel MOS transistors cut out of (100) and (110) wafers and produced in the same way, μF8 is 350,000, 310,000, respectively.
It was 0 Cri/V @ 8 e c.

Next, (111) with a carrier concentration of n~1015/cd
A p-channel MO8) transistor was manufactured using a PbTe wafer in the same manner as in the previous example except that the source and drain were formed using Tt ion implantation. The μFE was 230,000 cIvv·see at liquid He temperature. On the other hand, when formed on (100) and (110) wafers, μFg is 200,000 and 180,000c, respectively.
It was rl/v·sec.

Next, a ring oscillator with 31 stages of E/D MOS inverters was fabricated, with a p-type (11)PbTe-PbTe uni n-channel E-type MOS transistor as a driver and an n-channel p-type MO8) transistor as a load. Figure 2 shows the one-stage E/D MOS inverter.
A gate insulating film 221 is formed on the bTa wafer 21 as shown in FIG.
, 222 to form a gate current w1231, 232, and the source and drain are connected to n+fF by ion implantation.
24, to 243 are formed. Note that the load side is made into a D type by performing ion implantation into the channel region KBj.

From the obtained oscillation frequency of the ring oscillator, the switching delay time per stage is 70 p at the liquid He temperature.
sec is obtained from the zero-order BaF2 single crystal (11
1) Cut out a slice and polish the surface of this substrate well.
So, for this (111) PbTe g film single crystal 5000
X was grown heteroepitaxially. This PbTe1
A ring oscillator consisting of 45 stages of E/D MOS inverters as described above was formed on the L film, and the delay time per stage from the oscillation frequency was measured.
It was 0 psec.

In addition, a similar (] 11) PbTe thin film single crystal was separated into islands, and an n-channel MOS transistor and an n-channel MOS transistor were installed in each island region.
p-channel MO8) CM combined by forming transistors
A 27-stage OS inverter was constructed to form a ring oscillator. FIG. 3 shows the configuration of one stage of the CMOS inverter. That is, 3 is the (l l l) B&F2 single crystal substrate, which was grown heteroepitaxially on the 321t32z substrate and separated into islands (l l l
) PbTa thin film single crystal.

Each thin film single crystal, 92I +32z, is made p-type and n-type with a carrier concentration of 1015/cd by ion implantation, respectively.
After forming an r-) electrode 34H+342 thereon via an r-to insulating film 331+332, an n+ type layer 351 is formed by selectively i-ion implantation.

352, p+ type layer by selective Tt ion implantation, 96
．． ．． By sequentially forming 36° and wiring! +
It constitutes a CMOS inverter.

The delay time per stage measured from the oscillation frequency of this ring oscillator was so psec, and the product of delay time and power consumption was 50 fJ. By the way, (100)Pb
When a ring oscillator consisting of a similar CMOS inverter is constructed using Te thin film single crystal, the delay time per stage is 15 Qpsec, and the delay time/power consumption product is 48
It was fJ.

9- As mentioned above, in the case of a MOS transistor in which the channel region is tossed on the surface of a PbTe crystal, (111
By using ) planes, MOS () transistor circuits can maximize their operating speed.

In particular, according to the present invention, it is possible to maximize the high carrier mobility of 9% for both channels, and as clarified in the examples, when a CMOS inverter is configured, an n-channel E/D MOS inverter It is possible to realize high-speed operation that is almost the same as that of PbTe in lead chalcogenide, but the situation is the same for other types of PbS and Pb5e.

[Brief explanation of drawings]

The if diagram is a diagram showing an example of constructing a P-channel MO8) transistor using a (l l l) PbTe wafer.
The same figure shows an example of constructing an E/DMOS inverter. 11 * 21... (J, L l) PbTe single crystal wafer, 12.221 .222... Dirt insulating film, 1,9°23, .23 2... Gate
Denii σ, 141,142°241 + 24
2 + 24'A...n+ type layer, 31...(l
i1) BaF2'C' crystal substrate, 32. ,．． 92
2-...(111)PbTe thin film single crystal, 3B, ,
J32 ・r-to, insulating film, 341+ 342
...Kate electrode, 35 (, 352-n+ type layer, 36
1.362-p” type layer. 114 Patent attorney Takehiko Suzue 11- Figure 1 Figure 3

Claims (4)

[Claims] (1) In a semiconductor device formed by forming one or more MOS (MOS) transistors having a dirt electrode on the surface of a lead chalconide crystal via a dirt insulating film, it is possible to use a (ttB plane) as the crystal surface. A semiconductor device characterized by: (2) p-channel MO8) transistor and n-channel MO
8) The semiconductor device according to claim 1, wherein a di-complementary circuit is constructed of transistors. (3) The semiconductor device according to claim 1, wherein the lead chalconide crystal is a bulk single crystal. (4) The semiconductor device according to claim 1, wherein the lead chalcogenide crystal is a thin film single crystal grown biheteroaxially on a single crystal insulating substrate.