JPS5985574A - Double balancing circuit - Google Patents

Abstract

PURPOSE:To ensure the stable working of a double balancing circuit despite of the drop of power supply voltage and to reduce the noise by dividing the collector voltage of a transistor constituting a current mirror circuit into a prescribed level and using these divided voltages to the base bias of a differential paired transistors. CONSTITUTION:A resistance R10 is put between the collector of a transistor TRQ2 and the anode of a diode D1. The collector voltage of a TRQ2 is divided at the middle point of the joint between the R10 and the anode of the D1. If the power supply voltage VCC drops, the collector current of the TRQ2 is reduced. Thus the potential VB drops for the anode of the D1. In such a way sudden saturation of a differential pair TRQ11 and Q12 is prevented. As a result, the overall gain drop is gently decreased to ensure the stable working of a double balancing circuit even in a pressure reduction environment.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a double balance circuit, and particularly to improvements in its bias circuit.

[Technical background of the invention]

Conventionally, double-9 lance circuits (double-balanced differential amplifier circuits) have been widely used as analog signal amplifiers, such as in FM radio receiver multiplex circuits and quadrature FM demodulation circuits. .

Such a double-balanced circuit, for example, as shown in FIG.
+QI2 has second and third differential pair transistors Q21PQ22 and Q
The valley common emitters of 311Q3□ are connected correspondingly. Each collector of this second differential pair transistor Q21TQ22 is connected to a corresponding pair of output terminals Oa+O.
Similarly, the third differential pair transistor Q31
The valley collector of 1Q3□ is a pair of 111 Toko Ichiko Oa *
It is connected to ob. Above transistor Q
21+Qs+, each collector is connected to the power supply Vcc via a common load resistance Ra, and in the above 1.Lancestar Q221'Q32, each collector is connected to the power supply Vcc via a common load resistance Ra.
It is connected to the power supply Vcc via b.

Further, the first differential pair transistor. Each base of IIIQ12 has a first balanced input terminal IXa, I to which a non-inverting input signal and an inverting input signal are respectively supplied.
Connected to Xb. Each base of the second differential pair transistor Q211Q2□ is correspondingly connected to each base of the third differential pair transistor Q3□+Qs+, and the second differential pair transistor Q211Q2□ is connected to each base of the third differential pair transistor Q3□+Qs+, and the second are connected to the balanced input terminals IYa and IYb of the resistor Re.

It is connected to the power supply Vcc via Rd.

The base bias of each of the first differential pair transistors Q11 and Q12 can be supplied by the configuration described below.

The PNP transistor Q+ has its emitter connected to the power supply Vcc, and its base and emitter, which are commonly connected, are grounded via a constant current source Io. P that constitutes a current mirror circuit with this transistor Q1
The NP-type transistor Q2 has an emitter connected to the power supply Vcc, a base connected to the base of the transistor Q2, and a collector connected to a diode D1 with the polarity shown and a resistor R.
It is grounded through 1. The midpoint of the connection between the collector of the transistor Q2 and the diode is connected to the capacitor c1.
It is connected to the bases of the transistors Qll and Q12 via resistors R2 and R3 correspondingly.

Therefore, the current mirror circuit made up of the transistors Ql and Q2 in FIG. 1 supplies a current substantially equal to the constant current source Io current to the diode D1 and the resistor R1. The voltage drop across diode D and resistor R1 provides a correspondingly stable base bias for transistors Q1 and Q2 via resistors R2 and R3. That's it, the above capacitor C1
For example, it works to bypass noise components to ground. The resistor RO connected to the common emitter of the first differential pair transistor Qt++Q+□ is used in place of a constant current source especially for the purpose of reducing noise.

[Problems with background technology]

However, in the circuit of FIG. 1, the potential Va at the connection midpoint between the collector of the transistor Q2 and the diode D1 is stabilized with respect to the voltage fli of the power supply Vcc'il (voltage); In a reduced voltage state where the voltage decreases, the voltage between the collector and emitter of each of the first differential pair transistors Q+11Q12 decreases, causing the transistors Q111Q12 to become saturated and their gain to decrease rapidly. Power supply V
When the cc* pressure has decreased, the first balanced input terminal IXa
, When a large input is applied to IXb, transistor Q+
Since the collector-emitter voltage of 11Q'l□ is small, it becomes saturated and causes abnormal operation.

On the other hand, in order to stabilize the operation in a reduced voltage state, it is sufficient to reduce the voltage drop across the resistor R8, but it becomes impossible to suppress the common mode input due to noise, for example, which is supplied to the first balanced input terminals IXa and IXb. Therefore, the voltage drop across the resistor R8 must be a sufficiently large value compared to the thermal voltage VT.

Note that the thermal voltage VT is expressed as VT=kT/q, where k is the Delraman constant T is the absolute temperature, and q is the charge of the electron.

[Purpose of the invention]

The present invention was conceived in view of the above points, and an object of the present invention is to provide a good double balance circuit that operates stably even when the power supply voltage is lowered and has less noise.

[Summary of the Invention] The present invention connects the common emitters and vines of the second and third differential transistors to each collector side of the first differential pair transistor in a corresponding manner, and also connects a constant current source. and the first difference ! by a bias section having a current mirror circuit! In a double glance circuit that supplies each base bias to a pair of transistors and performs analog signal multiplication, the collector voltage of the transistor constituting the current mirror circuit is divided to a predetermined level and the first
The present invention is characterized by comprising means for setting a pace bias of the differential pair transistors.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows a double balance circuit according to the present invention. However, in FIG. 2, the same parts as in FIG. 1 are given the same reference numerals, and their explanations will be omitted.

That is, a resistor RIO1 is connected between the collector of the transistor Q2 and the anode of the diode D. The midpoint of the connection between the resistor RIO and the anode of the diode is where the voltage obtained by dividing the collector voltage of the transistor Q2 by the resistor RIO, the diode DI, and the resistor R1 can be derived, and the resistor R2 + R3 + capacitor One common end of C1 is connected.

In the double-balanced circuit having the above configuration, when the voltage decreases in which the power supply Vcc' voltage decreases, the collector current of the transistor Q2 decreases and the diode D,
The potential VB (that is, the bias voltage) of the anode decreases. Therefore, the 10th differential pair transistor Q111Q1
2 is prevented from suddenly becoming saturated, the double-balanced circuit shown in Figure 2 has a gradual and small drop in overall gain, and operates stably even under reduced voltage conditions. It is.

Here, if the voltage drops due to resistors Ro and RIQ are set to 700 mV and 300 mV K, respectively, then comparing the circuit in Figure 2 with the circuit in Figure 1, the circuit in Figure 2 has a voltage drop of 700 mV and 300 mV. For transistor QII
; hrui (lZtQ t□'s collector-emitter voltage VCE changes as shown by the solid line in FIG. 3. On the other hand, in the circuit of FIG. The collector-emitter voltage VCE of bright 1jQt2 changes as shown by the broken line in FIG.

According to this comparison, it is clear from Fig. 3 that in the circuit of Fig. 2, the collector-emitter voltage of transistors Q1□ to Q1□ changes gradually as the power supply Vcc voltage decreases. You can see that it works stably.

Furthermore, the circuit shown in FIG. 2 can sufficiently suppress the in-phase power applied to the first balanced input terminals IXa and IXb since the voltage drop caused by the resistor RO can be made sufficiently high with respect to the thermal voltage VT. This shows good low noise characteristics.

By the way, the power supply Vc at which the transistor Q2 becomes saturated
c [voltage is the saturation voltage of the trans-zoster Q2, the forward voltage of the diode D1, and the resistor R1+R1
0 is the sum of each voltage drop. The power supply Vcc voltage at which the transistors Q11 to Q12 become saturated is the sum of the saturation voltage of the transistors Q11 to Q12, the base-emitter voltage of the transistors Q211Q22 to Q311Q32, and the voltage drop across the resistor RO.

Therefore, if a transistor with a short-circuit between the pacer and the luctor is used as the diode D+, the forward voltage of the diode D and the trannostar Q211Q22 to Q311
The voltage between the base and emitter of Q32 is approximately equal, and the difference between the power supply Vcc voltage at which the transistor Q2 becomes saturated and the power supply Vcc voltage at which the first differential pair transistor Q+11Q+2 becomes saturated is the voltage of the resistor RIO. It will just fall. Accordingly, the resistance value of the resistor RIO may be appropriately set so as to obtain a desired drop pressure. Also, valley transistor Q211Q2□.

If the power supply voltage supplied to Q31PQ32 is lower than the power supply VCC voltage, the voltage drop across the resistor RIO may be increased accordingly.

Note that the present invention is not limited to the above-mentioned embodiment, and may be modified as shown in FIG. 4, for example. However, in FIG. 4, the same parts as in FIG. 2 are given the same reference numerals, and the explanation thereof will be omitted.

That is, the emitters of the transistors Ql and Q2 forming the current mirror circuit ↓.16]1η are connected to the power supply Vcc via corresponding resistors RII+R12 to reduce the influence of the Early effect. In place of the diode D, a transistor Q3 is used which connects the collector pads in common. Resistors R11IR12 are connected in series between the emitters of the first differential pair transistors Q+31QI4,
One end of the resistor R8 is connected to the midpoint between the resistors R11 and R12 to reduce noise.

It goes without saying that various other modifications and applications are possible without departing from the gist of the invention.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide an excellent double-balanced circuit that operates stably even when the power supply voltage is lowered and has less noise.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a conventional double balance circuit, Figure 2 is a circuit diagram showing a conventional double balance circuit.
The figure is a circuit diagram showing a double balance circuit according to the present invention, FIG. 3 is a diagram used to explain the effect of FIG. 2, and FIG. 4 is a diagram showing another embodiment. FIG. Qllll QI21 Q21P Q221 Qa++
Q3□+ Q I+Q2 , Qs ”・) Lansostar, Ro , R, ,,,,. R3+ RIon”'pR12”' Resistor, ■ o... Constant current source, = D1... Diode. Applicant's representative Patent Attorney Takehiko Suzue Figure 1 Figure 3 VCC [, VJ

Claims (1)

[Claims] On the collector side of each of the first differential pair transistors, each of the second and third differential pair transistors has 11 emitters.
In the double-balanced circuit, the bias section having a constant current source and a current mirror circuit supplies each pace bias to the first differential pair transistors to perform analog signal multiplication. 1. A double balance circuit comprising means for dividing the collector voltage of the transistors constituting the mirror circuit to a predetermined level and using the voltage as a base bias for the first differential pair transistors.