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JPS5980934A - Manufacture for semiconductor device - Google Patents

Manufacture for semiconductor device

Info

Publication number
JPS5980934A
JPS5980934A JP17188683A JP17188683A JPS5980934A JP S5980934 A JPS5980934 A JP S5980934A JP 17188683 A JP17188683 A JP 17188683A JP 17188683 A JP17188683 A JP 17188683A JP S5980934 A JPS5980934 A JP S5980934A
Authority
JP
Japan
Prior art keywords
circumferential
substrate
circumferential end
wafer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17188683A
Other languages
Japanese (ja)
Inventor
Katsunobu Kakizaki
柿崎 勝信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP17188683A priority Critical patent/JPS5980934A/en
Publication of JPS5980934A publication Critical patent/JPS5980934A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3046Mechanical treatment, e.g. grinding, polishing, cutting using blasting, e.g. sand-blasting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To reduce the generation of a displacement largely from a circumferential edge, and to decrease defects in a photoetching process by each forming rectilinear tapers from the surface and the back extending over the whole circumference of a wafer and forming the ends of both tapers in arcuate circumferential ends. CONSTITUTION:A semiconductor base body 40 has a circumferential surface as the surface 11, the back 12, an arcuate circumferential end surface 20 and rectilinear tapered surfaces 21, 21'. A circumferential end angle alpha at a section 22 formed by the surface 11 and the inclined plane 21 and an angle alpha' at a section 22' formed by the back 12 and the inclined plate 21' are brought to obtuse angles of 90 deg. or more. Circumferential end angles beta and beta' each formed by the arcuate circumferential end surface 20 and both inclined planes 21 and 21' are also brought to 90 deg. or more.

Description

【発明の詳細な説明】 本発明は、半導体装置の製造方法に関するものである。[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.

従来技術による半導体装置の製造に用いられている基板
の端部は第1図に示されている如き構造を有している。
The edge of a substrate used in the manufacture of semiconductor devices according to the prior art has a structure as shown in FIG.

即ち第1図は尚該基板の周端部の断面図であり、1及び
2は、各々当該基板の表面及び裏面、3は周端面、4及
び4′は尚該基板の表面1及び裏面2と周端面3により
て夫々形成される描該基板の「周端角」、5及びぎは周
端角部分以外の基板部分を夫々示している。周端角4及
び4/は図示の如く#1ぼ90’である。この様に従来
技術による半導体装置の製造に用いられる基板はほぼ9
0°の「周端角」を有していた。それ故、半導体装置製
造の際の熱処理(加熱冷却)によって。
That is, FIG. 1 is a sectional view of the peripheral edge of the substrate, where 1 and 2 are the front and back surfaces of the substrate, 3 is the peripheral edge, and 4 and 4' are the front 1 and back 2 of the substrate. The "circumferential edge angle" of the substrate formed by the circumferential edge surface 3 and the circumferential edge surface 3, respectively, and 5 and 5 respectively indicate the substrate portions other than the circumferential edge corner portion. The circumferential end angles 4 and 4/ are approximately 90' as shown. In this way, the number of substrates used in the manufacture of semiconductor devices using conventional technology is approximately 9.
It had a "peripheral edge angle" of 0°. Therefore, through heat treatment (heating and cooling) during semiconductor device manufacturing.

基板周端角4,4′と基板周端角取外の基板部分5゜5
/とに熱影響の差が生じ、その差によシ局部的な応力が
発生しく即ち応力が基板の端部に集中する)。
Board peripheral edge angles 4, 4' and the board portion where the board peripheral edge angle is removed 5゜5
A difference in thermal effects occurs between the substrate and the substrate, and this difference generates local stress (that is, the stress is concentrated at the edge of the substrate).

その応力によって周端角4.41から転位が発生する。Dislocation occurs from the circumferential edge angle 4.41 due to this stress.

かかる転位の発生は、基板又はウェファを大量に重ねて
処理するいわゆるバッチ処理の場合に特に顕著である。
The occurrence of such dislocations is particularly noticeable in so-called batch processing in which a large number of substrates or wafers are stacked and processed.

その転位はさらに周端角以外の基板部分5,5′へと進
行し、その結果半導体装置の電気的接合部であるP−N
接合の漏洩電流を増大させたり、或いは耐圧を劣化させ
たりする事が知られている。また、従来の半導体装置の
製造に用いられる上記基板の周端角4.4′の部分への
衝撃によっても当該周端角部分から転位が発生し。
The dislocation further advances to the substrate portions 5, 5' other than the peripheral edge angle, and as a result, the P-N which is the electrical junction of the semiconductor device
It is known that this increases the leakage current of the junction or deteriorates the withstand voltage. Furthermore, dislocations occur from the 4.4' edge angle portion of the substrate used in the manufacture of conventional semiconductor devices due to an impact thereon.

前述と同様の結果をもたらす事となる。そして。This will produce the same result as above. and.

当該角部分への衝撃により当該角部分が欠けた場合には
、その欠けた破片がパターン形成のための写真食刻を妨
げたシ或いはパターン形成に使用するマスクに損傷を与
えたシして、著しく不経済であり、かつ高い良品率を得
ることは、はなはだ困難である等の欠点があった。一方
第2図に示すような半導体基板(半導体ウェハー)では
上記欠点は除去される。すなわち、第2図において周端
面18は円弧状に形成されておシ2表面11と円弧状周
端面18が連結される部分19にそれらの面が々す周端
角αが存し、裏面12と周端面18が連結される部分1
9/に面12と面18がなす周端角dが存在する。周端
角α及びびは90°より大きい鈍角に形成されることは
勿論である。
If the corner portion is chipped due to an impact on the corner portion, the chipped pieces may have interfered with photo-etching for pattern formation or damaged the mask used for pattern formation. It has drawbacks such as being extremely uneconomical and extremely difficult to obtain a high yield of non-defective products. On the other hand, in a semiconductor substrate (semiconductor wafer) as shown in FIG. 2, the above-mentioned drawbacks are eliminated. That is, in FIG. 2, the circumferential end surface 18 is formed in an arc shape, and a circumferential end angle α between these surfaces exists in a portion 19 where the surface 11 of the rear surface 11 and the arc-shaped circumferential end surface 18 are connected. Portion 1 where and peripheral end surface 18 are connected
There is a circumferential edge angle d formed by the surfaces 12 and 18 at 9/. Of course, the circumferential edge angle α and the angle are formed to be obtuse angles larger than 90°.

一方半導体装置の製造方法において半導体基板(半導体
ウェハー)と写真蝕刻工程におけるマスクとの密着、剥
離が多く行なわれる。この剥離の際に半導体基板とマス
クとの間に気体を吹き入れて行なわれる場合が多いが第
2図の構造では上記工程の除に十分に作業性のある剥離
が行なわれない欠点がある。
On the other hand, in a method of manufacturing a semiconductor device, a semiconductor substrate (semiconductor wafer) and a mask are often brought into close contact and separated from each other in a photolithography process. This separation is often carried out by blowing gas between the semiconductor substrate and the mask, but the structure shown in FIG. 2 has the disadvantage that separation cannot be performed with sufficient workability beyond the above steps.

したがって本発明の目的は、上記全ての欠点を除去した
有効な半導体装置の製造方法を提供することである。
Therefore, an object of the present invention is to provide an effective method for manufacturing a semiconductor device that eliminates all of the above-mentioned drawbacks.

本発明の特徴は、半導体基板(半導体ウェハー)の全周
にわたってその断面形状は9表面および裏面からそれぞ
れ直線状のテーパが設けられ、該両テーパの先で円弧状
の周端となっておシ、この半導体基板に能動素子を設け
た半導体装置の製造方法にある。このような形状はたと
えば半導体基板を回転させ、所定形状の刃物、グライン
ダー等をあてることによりて形体することができる。
The feature of the present invention is that the cross-sectional shape of the semiconductor substrate (semiconductor wafer) has a linear taper from the front surface and the back surface, respectively, and the tip of both tapers forms an arc-shaped peripheral edge. , a method of manufacturing a semiconductor device in which an active element is provided on this semiconductor substrate. Such a shape can be formed, for example, by rotating the semiconductor substrate and applying a knife, a grinder, etc. of a predetermined shape to the semiconductor substrate.

本発明に使用される基体は以上の如き構造になっている
ので1本発明によれば、半導体装置製造の際の熱処理に
よる周端角から発生する転位が著しく減少し、又1周端
の衝撃を受ける部分の面積が広く形成されていることに
よって衝撃応力が実効的に小さくなり、転位の発生も8
(1以上減少し、更に又、基板の欠けの発生については
、はぼ196以下にすることが出来写真食刻工程での欠
陥を大幅に減少させることが出来た。以上説明したよう
に9本発明によれば基板周端からの転位発生を極めて大
幅に減少させ、写真食刻工程での欠陥を著しく減少させ
る事が出来るために、半導体装置の製造に於ける良品率
を格段に高くならしめる利点がある。また本発明による
半導体装置の漏洩電流は平均して一桁以上減少した。
Since the substrate used in the present invention has the above-described structure, according to the present invention, dislocations generated from the peripheral edge angle due to heat treatment during semiconductor device manufacturing are significantly reduced, and By forming a large area of the receiving part, the impact stress is effectively reduced, and the occurrence of dislocations is also reduced.
(The number of chippings on the substrate was reduced by more than 1. Furthermore, the number of chippings on the substrate was reduced to 196 or less, and the number of defects in the photolithography process was significantly reduced.As explained above, 9 chips According to the invention, it is possible to significantly reduce the occurrence of dislocations from the peripheral edge of the substrate, and to significantly reduce defects in the photolithography process, thereby significantly increasing the yield rate in the manufacture of semiconductor devices. Further, the leakage current of the semiconductor device according to the present invention has been reduced by more than an order of magnitude on average.

しかも本発明ではウェハー周辺表面にテーパーがついて
いるので写真食刻工程に於けるマスクとの接触時にマス
クへ傷をつける事がない〇又、当工程ではマスクとウェ
ハーの位置合せの為、マスクとウェハーを頻繁に密着さ
せたシ剥離させたシしなければならないが、この相反す
る密着性と剥離性とを兼合わせる為には、6エノ・−周
辺部表面にテーパーを付は密着〜剥離時のマスクルウェ
ハー間の気体等の出入を容易にさせる事が有効である。
Moreover, in the present invention, since the peripheral surface of the wafer is tapered, the mask will not be damaged when it comes into contact with the mask during the photolithography process.In addition, in this process, the mask and wafer are aligned, so the mask and wafer are aligned. The wafer must be frequently brought into close contact with the wafer and then peeled off. In order to achieve both adhesion and peelability, which are contradictory, it is necessary to taper the peripheral surface of the wafer. It is effective to facilitate the flow of gas, etc. between the maskle wafers.

又、各工程間のウェハーの移動はエアーベアリング等が
用いられるが、その際エアー中での抵抗が少い程容易に
移動させる事が出来る。
Further, air bearings or the like are used to move the wafer between each process, and the smaller the resistance in the air, the easier the movement.

そして本発明のような形状は流体力学上非常に抵抗が少
くなる。
The shape of the present invention provides extremely low resistance in terms of fluid dynamics.

又、上記効果は両面より直線テーパ状を設けただけのも
のよシも円周面が円弧状となりているのでより効果があ
る。しかし本発明は両面よシの直線テーパ状に円弧状の
形状が加わるので両面よりの直線テーパ状だけのものに
比して多少加工上のコストが高くなる。これは使用用途
により使い分ければよい。
Further, the above effect is more effective than simply providing a straight taper shape from both sides because the circumferential surface is arcuate. However, in the present invention, since an arcuate shape is added to the linearly tapered shape from both sides, the processing cost is somewhat higher than that of a linearly tapered shape from both sides. This can be used depending on the purpose of use.

次に本発明の実施例を第3図に示す。Next, an embodiment of the present invention is shown in FIG.

第3図は本発明に係る方法に使用する基体の更に他の例
を示す周端部分断面図である。基体4゜は表面11.裏
面121円弧状周端面20.直線状の傾斜面(テーパ面
)21,21/の如き周辺面を有している。図に於いて
表面11と傾斜面21のなす部分22の周端角α、裏面
12と傾斜面21′のなす部分2zの角びは90’以上
の鈍角にされている。円弧状周端角2oと傾斜面21及
び21′とが夫々なす周端角β及び〆も900以上であ
ることは言うまでもない。
FIG. 3 is a partial cross-sectional view of the peripheral end of still another example of the substrate used in the method according to the present invention. The base body 4° is the surface 11. Back surface 121 arc-shaped peripheral end surface 20. It has peripheral surfaces such as linear inclined surfaces (tapered surfaces) 21, 21/. In the figure, the circumferential edge angle α of the portion 22 formed by the front surface 11 and the inclined surface 21, and the angle of the portion 2z formed by the rear surface 12 and the inclined surface 21' are obtuse angles of 90' or more. Needless to say, the circumferential edge angle β and the angle formed by the arcuate circumferential edge angle 2o and the inclined surfaces 21 and 21' are also 900 or more.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図は従来技術の半導体ウェハーの端部
断面図であり、第3図は本発明の実施例の半導体ウェハ
ーの端部断面図である。 尚9図において1.11は表面、2.12は裏面。 3.18.20は端面、4.4’、αd、β〆は周端角
5.5′は基板の周端角部分以外の部分、 21.21
’は傾斜面、 30.40は基体(半導体ウェハー)で
ある。 187
1 and 2 are end cross-sectional views of a conventional semiconductor wafer, and FIG. 3 is an end cross-sectional view of a semiconductor wafer according to an embodiment of the present invention. In Figure 9, 1.11 is the front side, and 2.12 is the back side. 3.18.20 is the end face, 4.4', αd, β〆 is the peripheral edge angle 5.5' is the part other than the peripheral edge corner part of the board, 21.21
' is an inclined surface, and 30.40 is a base (semiconductor wafer). 187

Claims (1)

【特許請求の範囲】 半導体基板の全周にわたりてその断面形状は。 表面および裏面からそれぞれ直線状のテーパが設けられ
、該両テーパの先で円弧状の周端となっており、該半導
体基板に能動素子を設けたことを特徴とする半導体装置
の製造方法。
[Claims] The cross-sectional shape of the semiconductor substrate is as follows. 1. A method of manufacturing a semiconductor device, wherein linear tapers are provided from the front surface and the back surface, and arcuate peripheral ends are formed at the tips of the tapers, and an active element is provided on the semiconductor substrate.
JP17188683A 1983-09-16 1983-09-16 Manufacture for semiconductor device Pending JPS5980934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17188683A JPS5980934A (en) 1983-09-16 1983-09-16 Manufacture for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17188683A JPS5980934A (en) 1983-09-16 1983-09-16 Manufacture for semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP10067574A Division JPS5127772A (en) 1974-09-02 1974-09-02 Handotaisochi no seizohoho

Publications (1)

Publication Number Publication Date
JPS5980934A true JPS5980934A (en) 1984-05-10

Family

ID=15931615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17188683A Pending JPS5980934A (en) 1983-09-16 1983-09-16 Manufacture for semiconductor device

Country Status (1)

Country Link
JP (1) JPS5980934A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62263626A (en) * 1986-05-09 1987-11-16 Mitsubishi Metal Corp Semiconductor wafer
JP2015140270A (en) * 2014-01-28 2015-08-03 グローバルウェーハズ・ジャパン株式会社 silicon wafer
CN111463111A (en) * 2020-05-06 2020-07-28 哈尔滨科友半导体产业装备与技术研究院有限公司 Nondestructive single chip with edge convenient to identify, marking method thereof and special grinding wheel

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62263626A (en) * 1986-05-09 1987-11-16 Mitsubishi Metal Corp Semiconductor wafer
JPH079873B2 (en) * 1986-05-09 1995-02-01 三菱マテリアル株式会社 Semiconductor wafer
JP2015140270A (en) * 2014-01-28 2015-08-03 グローバルウェーハズ・ジャパン株式会社 silicon wafer
WO2015114974A1 (en) * 2014-01-28 2015-08-06 グローバルウェーハズ・ジャパン株式会社 Silicon wafer
CN105814245A (en) * 2014-01-28 2016-07-27 环球晶圆日本股份有限公司 Silicon wafer
CN108461384A (en) * 2014-01-28 2018-08-28 环球晶圆日本股份有限公司 Silicon wafer
CN105814245B (en) * 2014-01-28 2018-09-04 环球晶圆日本股份有限公司 Silicon wafer
CN108461384B (en) * 2014-01-28 2022-10-28 环球晶圆日本股份有限公司 Silicon wafer
CN111463111A (en) * 2020-05-06 2020-07-28 哈尔滨科友半导体产业装备与技术研究院有限公司 Nondestructive single chip with edge convenient to identify, marking method thereof and special grinding wheel

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