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JPS598070B2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS598070B2
JPS598070B2 JP51036040A JP3604076A JPS598070B2 JP S598070 B2 JPS598070 B2 JP S598070B2 JP 51036040 A JP51036040 A JP 51036040A JP 3604076 A JP3604076 A JP 3604076A JP S598070 B2 JPS598070 B2 JP S598070B2
Authority
JP
Japan
Prior art keywords
electrode
type
charge
layer
charge transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP51036040A
Other languages
Japanese (ja)
Other versions
JPS52120688A (en
Inventor
正和 青木
信弥 大場
征治 久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP51036040A priority Critical patent/JPS598070B2/en
Publication of JPS52120688A publication Critical patent/JPS52120688A/en
Publication of JPS598070B2 publication Critical patent/JPS598070B2/en
Expired legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D44/00Charge transfer devices
    • H10D44/40Charge-coupled devices [CCD]
    • H10D44/45Charge-coupled devices [CCD] having field effect produced by insulated gate electrodes 
    • H10D44/472Surface-channel CCD

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  • Solid State Image Pick-Up Elements (AREA)

Description

【発明の詳細な説明】 本発明は、半導体中の多数キャリアを情報源として順次
移送する電荷移送装置、とくに新規な電極構造をもつた
電荷移送装置、およびその製造方法に関するものである
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge transfer device that sequentially transfers majority carriers in a semiconductor as an information source, and particularly to a charge transfer device having a novel electrode structure and a method for manufacturing the same.

以下に述べる従来例の説明、本発明の原理および実施例
の説明においては、電荷移送装置として、おもに半導体
を基板とし、この基板上に形成された基板とは導電型の
異なる半導体層中の多数キャリアを情報源とする電荷移
送装置を用いるが、これはたとえば絶縁物など半導体以
外のものを基板とし、この上に形成された半導体層中の
多数キャリアを情報源とする電荷移送装置などであつて
もまつたく同様に適用できる。
In the explanation of the conventional example, the principle of the present invention, and the embodiments of the present invention described below, a semiconductor is used as a substrate as a charge transfer device, and many of the semiconductor layers formed on this substrate have a conductivity type different from that of the substrate. A charge transfer device that uses carriers as an information source is used, but this is, for example, a charge transfer device that uses a substrate other than a semiconductor such as an insulator and uses majority carriers in a semiconductor layer formed on the substrate as an information source. It can be applied in the same way.

また、以下の説明では、電荷移送装置は電子を情報源と
するが、これは電荷の極性、半導体の導電形および電位
関係を逆にすることにより、正孔を情報源とする電荷移
送装置にも、まつたく同様に適用できる。
In addition, in the following explanation, the charge transfer device uses electrons as the information source, but by reversing the polarity of the charge, the conductivity type of the semiconductor, and the potential relationship, the charge transfer device uses holes as the information source. can also be applied in the same way.

第1図は従来の多数キャリアを情報源とする電荷移送装
置(多数キャリア形電荷移送装置:BulkCharg
e−transferDevice)以下BCDと略す
)の断面構造と、BCDの電荷移送特性を最適にするチ
ャネル電位の関係を説明する図である。
Figure 1 shows a conventional charge transfer device using majority carriers as an information source (BulkChar).
FIG. 2 is a diagram illustrating the relationship between the cross-sectional structure of an e-transfer device (hereinafter abbreviated as BCD) and the channel potential that optimizes the charge transfer characteristics of the BCD.

図において、1は基板となるp形シリコン(Si)結晶
、2は基板1上に形成され、チャネルを形成するn形S
i層、3はn形Si層2の上に形成されたSiO2膜、
4はSiO2膜3中に離隔して埋込まれている第1の電
極となる多結晶Si電極、5は第1種の電極4の間隙部
のSiO2膜上を覆う、アルミニウム(Al)からなる
第2種の電極である。
In the figure, 1 is a p-type silicon (Si) crystal that serves as a substrate, and 2 is an n-type S crystal formed on the substrate 1 to form a channel.
i-layer 3 is a SiO2 film formed on n-type Si layer 2;
4 is a polycrystalline Si electrode which is a first electrode embedded in the SiO2 film 3 at a distance, and 5 is made of aluminum (Al) and covers the SiO2 film in the gap between the first type electrodes 4. This is the second type of electrode.

第1図に示した構造では、チヤネルとなるn形Si層2
を完全に空乏化するに最低限必要な電圧VO(絶対値で
考えることにする)は、各電極でほとんど同一であるの
で、いま各電極6〜11に直流レベルもパルス振幅も同
じ駆動パルスを印加すると、チヤネル電位に方向性が乏
しく、情報源となる多数キヤリア(以後信号電荷(図で
は斜線で示す)と呼ぶ)は同図bに示すように一部逆流
し正常な動作をしない。
In the structure shown in FIG. 1, an n-type Si layer 2 serving as a channel
Since the minimum required voltage VO (considered in terms of absolute value) to completely deplete is almost the same for each electrode, we now apply a driving pulse with the same DC level and pulse amplitude to each electrode 6 to 11. When applied, the channel potential has poor directionality, and the majority carriers (hereinafter referred to as signal charges (indicated by diagonal lines in the figure)), which serve as information sources, partially flow backwards and do not operate normally, as shown in Figure b.

この現象を防ぐためには、通例信号電荷の蓄積を行なう
第1種の電極7,9,11に印加する駆動パルスP1と
、通例スイツチとして用いる第2種の電極6,8,10
,に印加する駆動パルスP2との間に直流バイアスを印
加し、たとえば振幅10Vの駆動パルスを考えるときに
の電位関係でBCDを1駆動すればよいことになる。
In order to prevent this phenomenon, it is necessary to apply a driving pulse P1 to the first type electrodes 7, 9, 11, which normally accumulate signal charges, and to apply a driving pulse P1 to the second type electrodes 6, 8, 10, which are usually used as switches.
, and the drive pulse P2 applied to the drive pulse P2, for example, it is sufficient to drive BCD by 1 based on the potential relationship when considering a drive pulse with an amplitude of 10V.

しかしこの方法は、アース電位(0V)を除いて3個の
電源が必要となり実用的でない。第1図cは逆に駆動パ
ルス間に直流バイアスをかけ過ぎた場合を示す。
However, this method requires three power supplies other than the ground potential (0V), which is not practical. On the other hand, FIG. 1c shows the case where too much DC bias is applied between the drive pulses.

図かられかるように、こんどは電極9と11の間にポテ
ンシヤル障壁ができて信号電荷の一部が移送されないこ
とになりBCDの特性が劣化する。第1図dは、同図b
(5Cの中間であり、BCDの特性が良好となる状態で
ある。
As can be seen from the figure, a potential barrier is now formed between electrodes 9 and 11, and a portion of the signal charge is not transferred, resulting in deterioration of the BCD characteristics. Figure 1 d is the same figure b
(It is in the middle of 5C, and the BCD characteristics are good.

第1種の電極11下のチヤネル電位と、第2種の電極1
0下のチヤネル電位との差をVO6とすると、以上の議
論から 1駆動パルス振幅V との間に)
CP の関係が存在すればよいことが判る。
Channel potential under the first type electrode 11 and second type electrode 1
If the difference from the channel potential below 0 is VO6, then from the above discussion, the difference between 1 drive pulse amplitude V)
It turns out that it is sufficient if the relationship CP exists.

ここで、BCDを4相の駆動パルスで駆動するときには
第1図dのようにV。
Here, when driving the BCD with four-phase driving pulses, the voltage is V as shown in FIG. 1d.

。を小さくしておいても、駆動パルスの立ち上り時間(
5〜20nsec位)の間に大部分の電荷が移送されて
しまうので電荷が逆流する心配はなく、むしろ扱いうる
信号電荷量が多くなるので利点が大きいが、もしBCD
を2相の,駆動パルス(電極8および9に同一の駆動パ
ルス、6,7,10および11に別の駆動パルス、合計
2種類)で駆動するときには、!:f嬰営益小賛ヱ隣闇
t事瓜且ZLh議、^祖h二る信号電荷量を多くするに
はが最適となる。
. Even if you keep it small, the rise time of the drive pulse (
Since most of the charge is transferred within a period of about 5 to 20 nsec, there is no need to worry about the charge flowing backwards, and the advantage is that the amount of signal charge that can be handled increases.
When driven with two-phase drive pulses (same drive pulse for electrodes 8 and 9, different drive pulses for electrodes 6, 7, 10, and 11, two types in total), ! :The best way to increase the amount of signal charge is to increase the amount of signal charge.

VOOがこの点からずれると、上記移送時間か又は信号
電荷量のどちらかが不足になるからである。ただしこれ
は、駆動すべき周波数と、移送すべき信号電荷量に対す
る仕様いかんvでは正確に。
This is because if VOO deviates from this point, either the transfer time or the amount of signal charge becomes insufficient. However, this is accurate depending on the specifications for the frequency to be driven and the amount of signal charge to be transferred.

o−ー玉である必要はないことはもちろんである。さて
上記(1)あるいは(2)式のような条件をチヤネル内
に作り出すべく、駆動パルス間に直流バイアスを印加す
ることは、電源数を増し、直流バイアス調整を必要とす
るなど、BCDのシステム実装上、その取扱いを著しく
複雑にしており、BCDの応用上大きな障害となつてい
る。
Of course, it does not have to be an o-ball. Now, applying a DC bias between drive pulses in order to create conditions such as the above equations (1) or (2) within the channel requires an increase in the number of power supplies, the need for DC bias adjustment, etc., and the BCD system In terms of implementation, handling is extremely complicated, and this is a major obstacle in the application of BCD.

本発明の目的は、上述した問題点を解消した装置を提供
することである。
An object of the present invention is to provide a device that eliminates the above-mentioned problems.

本発明は、上記の目的を達成するために、電荷移送装置
の2種類の電極、すなわち、情報源としてのキヤリアの
蓄積を行なう第1種の電極(以下キヤリア蓄積電極と呼
ぶ)とスイツチの役目を果たす第2種の電極(以下キヤ
リア移送電極と呼ぶ)のうち、キヤリア移送電極の長さ
をキヤリア蓄積電極の長さより短かいものとし、かつ、
キヤリア移送電極の電極とゲート酸化膜との界面がキヤ
リア蓄積電極とゲート酸化膜との界面より電荷移送路と
なる半導体基板または半導体層裏面に近い位置にあるよ
うに形成することにより、駆動パルス間に直流バイアス
を印加しなくとも、BCDのチヤネルに前記(1)ある
いは(2)式の関係を得、かつチヤネルのポテンシヤル
を容易に制御できるような電極を得ることを可能にする
ものであつて、これにより、使用電源数の少ない、取扱
いの容易な、高集積度、かつ高速駆動可能な電荷移送装
置を実現するものである。
In order to achieve the above object, the present invention utilizes two types of electrodes of a charge transfer device, namely, a first type electrode (hereinafter referred to as carrier storage electrode) that stores carriers as an information source and a switch role. Among the second type of electrodes (hereinafter referred to as carrier transfer electrodes), the length of the carrier transfer electrode is shorter than the length of the carrier storage electrode, and
By forming the interface between the carrier transfer electrode and the gate oxide film to be closer to the semiconductor substrate or the back surface of the semiconductor layer, which serves as a charge transfer path, than the interface between the carrier storage electrode and the gate oxide film, the gap between the drive pulses is reduced. It is possible to obtain an electrode that can obtain the relationship of formula (1) or (2) above in the channel of a BCD and easily control the potential of the channel without applying a DC bias to the BCD channel. As a result, a charge transfer device that uses a small number of power supplies, is easy to handle, has a high degree of integration, and can be driven at high speed is realized.

以下本発明を実施例によつて説明する。The present invention will be explained below with reference to Examples.

第2図の本発明の一実施例を示すものであつて図中21
は基板となるp形S1、22はチヤネルを形成するn形
Si層、23はn形Si層22の上に形成されたSiO
2膜、24はSiO2膜23中に離隔して埋込まれてい
るキヤリア蓄積電極となる多結晶Si電極、25は第1
種の電極24に比べてn形Si層22の裏面に近づけて
形成されているキヤリア移送電極となるAl電極である
This figure shows an embodiment of the present invention shown in FIG.
22 is a p-type Si layer forming a channel, and 23 is a SiO layer formed on the n-type Si layer 22.
2 film, 24 is a polycrystalline Si electrode which becomes a carrier storage electrode and is embedded in the SiO2 film 23 at a distance, and 25 is a first polycrystalline Si electrode.
This is an Al electrode that serves as a carrier transport electrode and is formed closer to the back surface of the n-type Si layer 22 than the seed electrode 24 .

同図に示すごとく、キヤリア移送電極25をキヤリア蓄
積電極24にくらべてn形Si層22の裏面に近づけて
形成すると、n形Si層を完全に空乏化するに最低限必
要な、キヤリア移送電極に印加すべき電圧VO2を、キ
ヤリア蓄積電極に印加すべき電圧VOlにくらべて小さ
くすることができるので、同一の直流レベルで同一振幅
の駆動パルスによつて駆動しても、チヤネル電位に方向
性ができ、正常な動作を行なわせることができる。ここ
で上記n形Si層を完全に空乏化するに最低限必要な電
圧V。l,V62(総称してVOとする)の差は、同一
電圧を印加してキヤリア蓄積電極及びキヤリア移送電極
の下のn形Sl層を完全に空乏化させたときのチヤネル
電位の差にほぼ等しく、したがつて(1)あるいは(2
)式の条件を満足するためには、あるいは を満足するように、キヤリア移送電極25をn形Si裏
面に近づければよい。
As shown in the figure, when the carrier transfer electrode 25 is formed closer to the back surface of the n-type Si layer 22 than the carrier storage electrode 24, the carrier transfer electrode 25 is formed closer to the back surface of the n-type Si layer 22 than the carrier storage electrode 24. Since the voltage VO2 to be applied to the carrier storage electrode can be made smaller than the voltage VOl to be applied to the carrier storage electrode, there is no directivity in the channel potential even when driven by drive pulses of the same amplitude at the same DC level. This allows normal operation to occur. Here, the minimum voltage V is required to completely deplete the n-type Si layer. The difference between l and V62 (collectively referred to as VO) is approximately the difference in channel potential when the same voltage is applied to completely deplete the n-type Sl layer under the carrier storage electrode and the carrier transport electrode. equal, so (1) or (2
) In order to satisfy the condition of the expression (or), the carrier transfer electrode 25 should be brought close to the back surface of the n-type Si.

ここで前記のように(3)式は4相の駆動パルスでBC
Dを駆動する場合であり、(4)式はとくに2相の駆動
パルスの場合の最適条件である。ただし2相駆動の場合
も正確にV。
Here, as mentioned above, equation (3) is expressed by BC with four-phase drive pulses.
This is the case when driving D, and equation (4) is the optimum condition especially in the case of two-phase drive pulses. However, even in the case of two-phase drive, the voltage is exactly V.

l−VO2= 0Pでなくともよいことは前述の通りで
ある。上記V。
As mentioned above, it is not necessary that l-VO2=0P. V above.

次のようにして表わされる。ただしVFB: n形Si
層表面のフラツトバンド電圧φ8:n形のSi層を丁度
すべて空乏化したときの表面電位(チヤネル内の信号電
荷に対して最も電位の低い点から表面までの電位差)V
OX:SiO2に印加される電圧 さらにφS,Oxは次のように表わされる。
It is expressed as follows. However, VFB: n-type Si
Flat band voltage on the layer surface φ8: Surface potential when the n-type Si layer is completely depleted (potential difference from the point with the lowest potential relative to the signal charge in the channel to the surface) V
The voltage applied to OX:SiO2, φS, and Ox are expressed as follows.

φs二一4−Fdx″n(x)Dx(6)ただしq:電
荷素量(1.6×10−19クーロン)ε,i:Siの
誘電率(1.0×10−12フアラツド/C77!)ε
0X: SlO2の誘電率(3.4X10−13フアラ
ツド/CTIL)TOx:電極下のSiO2膜厚(c!
n)d:n形Si層表面からチヤネル内で信号電荷に対
する電位が最も低い点までの距離((177!)x:n
形Si層表面から深さ方向へ測距離(CTIL)n(x
):n形Si層内の不純物濃度(C!!L−3)したが
つて上記(3)〜(7)式を用いて、n形Si層裏面ま
での各電極からの距離の差Δlに対する条件を求めるこ
ともできる。
φs214−Fdx″n(x)Dx(6) where q: elementary charge (1.6×10−19 coulombs) ε, i: permittivity of Si (1.0×10−12 farads/C77 !)ε
0X: Dielectric constant of SlO2 (3.4X10-13 farad/CTIL) TOx: Thickness of SiO2 film under the electrode (c!
n) d: Distance from the n-type Si layer surface to the point with the lowest potential for signal charges in the channel ((177!) x: n
Distance measurement (CTIL) n(x
): Impurity concentration in the n-type Si layer (C!!L-3) Therefore, using equations (3) to (7) above, the difference Δl in distance from each electrode to the back surface of the n-type Si layer is calculated. You can also ask for conditions.

ここで駆動パルスが4相のときには、BCDの移送効率
および扱いうる最大信号電荷量の両面からみたVO,−
Here, when the drive pulse is four-phase, VO, -
.

2の最適条件が約1〜約4であることが実験よりわかつ
ている。
Experiments have shown that the optimum condition for 2 is about 1 to about 4.

したがつてたとえばTOx〜10−5儂n形Si層がガ
ウス分布をしていて、キヤリア蓄積電極下でn(0)−
2〜5×1016CfL−3、n形Si層全体の深さが
約10−4(:Tn..d?5×10−5cm1キヤリ
ア移送電極下はほぼキヤリア蓄積電極下のn形Si層を
表面側からΔlだけ削除しただけの分布のときにには、
Δlの最適値は200λ〜2000人であることがわか
る。第3図は本発明の別の実施例であつて、41はp形
Si基板、42はチヤネル形成するn形Si層、43は
n形Si層42の上に形成されたSiO2膜、44はS
iO2膜43中に離隔して埋込まれている第1種の電極
となる多結晶Si電極、45はキヤリア蓄積電極44に
比べてn形Si層裏面に近づけて形成されているキヤリ
ア移送電極となるAl電極である。
Therefore, for example, if TOx~10-5 the n-type Si layer has a Gaussian distribution and the n(0)-
2 to 5 x 1016CfL-3, the total depth of the n-type Si layer is approximately 10-4 (: Tn. When the distribution is just deleted by Δl from the side,
It can be seen that the optimum value of Δl is 200λ to 2000 people. FIG. 3 shows another embodiment of the present invention, in which 41 is a p-type Si substrate, 42 is an n-type Si layer forming a channel, 43 is a SiO2 film formed on the n-type Si layer 42, and 44 is a p-type Si substrate. S
A polycrystalline Si electrode serving as a first type electrode is embedded in the iO2 film 43 at a distance, and a carrier transport electrode 45 is formed closer to the back surface of the n-type Si layer than the carrier storage electrode 44. This is an Al electrode.

第2図や第3図に示したようなキヤリア移送電極をキヤ
リア蓄積電極に比べてn形Si層22ないし42の裏面
へ近づけた構造の電極は、上記のように駆動パルス間の
直流バイアスを除去せしめる効果だけでなく、キヤリア
移送電極下のn形Si層内の電位が、両隣りのキヤリア
蓄積電極下のn形Si層内の電位の影響を受けて変動す
るよ・うなことを防ぎ、キヤリア移送電極によつてその
下のn形Si層を低い電圧でも十分制御でき、容易にス
イツチとして作動させうる効果を兼ねそなえている。
As shown in FIGS. 2 and 3, an electrode with a structure in which the carrier transport electrode is closer to the back surface of the n-type Si layer 22 to 42 than the carrier storage electrode can reduce the DC bias between drive pulses as described above. In addition to the removal effect, it also prevents the potential in the n-type Si layer under the carrier transport electrode from fluctuating due to the influence of the potential in the n-type Si layer under the carrier storage electrodes on both sides. The carrier transport electrode allows the underlying n-type Si layer to be sufficiently controlled even at a low voltage, and has the effect of easily operating as a switch.

とくに第2図、第3図に示したような構造では、情報源
としてのキヤリアの蓄積はキヤリア蓄積電極で行ない、
キヤリア移送電極は単にスイツチとして用いることが一
般的であつて、キヤリアの移送時間を短縮する上で、キ
ヤリア移送電極は短かい程良好な特性が得られるので、
キヤリア移送電極はその電極長を短縮することが装置の
特性上望ましい。この場合上記のようなキヤリア蓄積電
極下のN8Si層の電位からの影響は、これを十分排除
して、キヤリア移送電極を安定して動作させる必要があ
る。この効果は、キヤリア移送電極をn形Si層の裏面
に近づければ近づける程大きい訳であるが、他方(3)
〜(7)式に示したような制限が、その距離の差Δ!=
2,−12に与えられており、場合によつては、キヤリ
ア蓄積電極下からの影響を完全には排除できない場合も
ありうる。第3図に示した実施例は、このような困難を
解決するものであつて、キヤリア蓄積電極、キヤリア移
送電極からn形Si層裏面までの距離の差Δlには上記
のような制限を加えたまま、n形Si層の裏面自体にも
、その上部の電極の凹凸に応じて凹凸をつけ、キヤリア
蓄積電極のn形Si層からの影響によるキヤリア移送電
極下のn形Si層における電位変動を十分抑えるもので
あり、これによつて使用電源の少ない高集積度、低電圧
駆動可能なBCDを得ることができる。
In particular, in the structures shown in Figures 2 and 3, carriers as an information source are stored at carrier storage electrodes.
The carrier transfer electrode is generally used simply as a switch, and in order to shorten the carrier transfer time, the shorter the carrier transfer electrode, the better the characteristics.
Due to the characteristics of the device, it is desirable to shorten the length of the carrier transport electrode. In this case, it is necessary to sufficiently eliminate the influence of the potential of the N8Si layer under the carrier storage electrode as described above to ensure stable operation of the carrier transport electrode. This effect becomes greater as the carrier transfer electrode is brought closer to the back surface of the n-type Si layer, but on the other hand (3)
~The limit as shown in equation (7) is the distance difference Δ! =
2, -12, and in some cases, it may not be possible to completely eliminate the influence from below the carrier storage electrode. The embodiment shown in FIG. 3 solves this difficulty by adding the above-mentioned restrictions to the distance difference Δl from the carrier storage electrode and the carrier transport electrode to the back surface of the n-type Si layer. In addition, the back surface of the n-type Si layer itself is also made uneven according to the unevenness of the upper electrode, and potential fluctuations in the n-type Si layer under the carrier transport electrode due to the influence from the n-type Si layer of the carrier storage electrode are created. As a result, it is possible to obtain a BCD that uses less power, has a high degree of integration, and can be driven at a low voltage.

ただし第3図の実施例のような場合には、キヤリア蓄積
電極とキヤリア移送電極の中間部分を信号電荷が通過す
るに支障ない程度のn形Si層を確保して、これを切断
しないように注意する必要がある。
However, in the case of the embodiment shown in Fig. 3, it is necessary to ensure that there is enough n-type Si layer to allow the signal charge to pass through the intermediate portion between the carrier storage electrode and the carrier transfer electrode, and to avoid cutting this layer. You need to be careful.

以上述べた本発明の実施例においては、半導体としては
Sil絶縁膜としてはSiO2膜、電極としては多結晶
SilまたはAlを用いたが、これらの材質およびその
形盛方法は、上記の説明に用いられたものに限定される
わけではない。
In the embodiments of the present invention described above, a SiO2 film was used as the Si insulating film as the semiconductor, and polycrystalline Sil or Al was used as the electrode. It is not limited to what is given.

たとえば、電極を形成する多結晶SiおよびAlは、こ
れが同じ材質であつてもよく、各々他の導電物質、たと
えば、タンタル(Ta)、タングステン(W)、モリブ
デン(MO)などの金属およびこれらの組合せを用いて
もよい。
For example, polycrystalline Si and Al that form the electrodes may be the same material, and each may be made of other conductive materials, such as metals such as tantalum (Ta), tungsten (W), and molybdenum (MO), and these materials. Combinations may also be used.

また、絶縁膜としてはSiO2の他にアルミナ(Al2
O5)、窒化珪素(Si3N4)、などおよびこれらの
複合膜を用いることができ、また、半導体としてSiを
用いた場合について述べたが、これもSiに限らず、半
導体であれば何でもよく、たとえば、ゲルマニウム(G
e)やさらにはガリウム・ヒ素(GaAs)などの複合
半導体を用いてもまたこれらを組合わせて用いても同様
な目的を達成することができる。以上説明したように、
本発明によれば、キヤリア蓄積電極に比べてキヤリア移
送電極をチヤネルとなる半導体層裏面に近づけることに
より、BCDの駆動パルス間の直流バイアスを除去し、
電源数を減少することができ、また、キヤリア移送電極
が、短かい電極長、低い駆動電圧の場合にも、その直下
のチヤネルを十分に制御することができ、これに伴い、
高密度で低電圧駆動の可能な、高周波特性の優れた多数
キヤリア形電荷移送装置を得ることができるなど半導体
装置の性能向上に著しい効果があることがわかる。
In addition to SiO2, alumina (Al2
O5), silicon nitride (Si3N4), etc., and composite films thereof can be used. Also, although we have described the case where Si is used as a semiconductor, this is not limited to Si, and any semiconductor may be used. For example, , germanium (G
The same objective can be achieved by using composite semiconductors such as e) or gallium arsenide (GaAs), or by using a combination of these. As explained above,
According to the present invention, by bringing the carrier transfer electrode closer to the back surface of the semiconductor layer serving as the channel than the carrier storage electrode, the DC bias between the driving pulses of the BCD is removed.
The number of power supplies can be reduced, and the carrier transfer electrode can sufficiently control the channel immediately below it even with short electrode lengths and low drive voltages, and accordingly,
It can be seen that the present invention has a remarkable effect on improving the performance of semiconductor devices, such as by being able to obtain a multi-carrier type charge transfer device that can be driven at high density and at low voltage and has excellent high frequency characteristics.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来の多数キヤリア形電荷移送装置の構造な
らびにその電荷移送特性を最適にするチヤネル電位の関
係を説明する図、第2図および第3図はそれぞれ本発明
の実施例の構造を示す図である。
FIG. 1 is a diagram illustrating the structure of a conventional multi-carrier charge transfer device and the relationship between channel potentials that optimize its charge transfer characteristics, and FIGS. 2 and 3 respectively illustrate the structure of an embodiment of the present invention. FIG.

Claims (1)

【特許請求の範囲】[Claims] 1 基板上に形成された上記基板とは電気的に絶縁され
た一導電形半導体層と、該半導体層上に絶縁膜を介して
順次配列された複数個の電極とをそなえ、情報源として
の上記半導体層中の電荷キャリアを上記電極下において
順次蓄積および移送させる電荷移送装置において、上記
電極は電荷蓄積電極と、該電荷蓄積電極の上流側に隣接
する電荷移送電極からなり、上記電荷移送電極の電極長
を上記電荷蓄積電極の電極長より短かいものとするとと
もに、上記電荷移送電極と上記絶縁膜との界面が上記電
荷蓄積電極と上記絶縁膜との界面より上記半導体層の裏
面に近い位置にあるものとし、上記半導体層を完全に空
乏化するために上記各電極に最少限印加すべき電圧の絶
縁値をV_c、上記電荷蓄積電極におけるV_cをV_
c_1、上記電荷移送電極におけるV_cをV_c_2
、上記電荷移送装置を駆動する駆動パルスの振幅をV_
c_pとしたときに、0V<V_c_1−V_c_2<
V_c_pであることを特徴とする半導体装置。
1 The substrate formed on the substrate includes a semiconductor layer of one conductivity type that is electrically insulated from the substrate, and a plurality of electrodes that are sequentially arranged on the semiconductor layer with an insulating film interposed therebetween, and serves as an information source. In a charge transfer device that sequentially stores and transfers charge carriers in the semiconductor layer under the electrode, the electrode includes a charge storage electrode and a charge transfer electrode adjacent to the upstream side of the charge storage electrode, and the charge transfer electrode is shorter than the electrode length of the charge storage electrode, and the interface between the charge transfer electrode and the insulating film is closer to the back surface of the semiconductor layer than the interface between the charge storage electrode and the insulating film. The insulation value of the minimum voltage that should be applied to each electrode to completely deplete the semiconductor layer is V_c, and V_c at the charge storage electrode is V_
c_1, V_c at the charge transfer electrode is V_c_2
, the amplitude of the driving pulse for driving the charge transfer device is V_
When c_p, 0V<V_c_1−V_c_2<
A semiconductor device characterized in that V_c_p.
JP51036040A 1976-04-02 1976-04-02 semiconductor equipment Expired JPS598070B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP51036040A JPS598070B2 (en) 1976-04-02 1976-04-02 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP51036040A JPS598070B2 (en) 1976-04-02 1976-04-02 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS52120688A JPS52120688A (en) 1977-10-11
JPS598070B2 true JPS598070B2 (en) 1984-02-22

Family

ID=12458586

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51036040A Expired JPS598070B2 (en) 1976-04-02 1976-04-02 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS598070B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62188081A (en) * 1987-01-14 1987-08-17 Hitachi Maxell Ltd Magnetic disk container
JPH0736475Y2 (en) * 1987-05-14 1995-08-16 阪神エレクトリック株式会社 Inverter device

Also Published As

Publication number Publication date
JPS52120688A (en) 1977-10-11

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