JPS5972256A - Multiple circuit high-speed communication controller - Google Patents

Abstract

PURPOSE:To shorten the latency time of a high-speed microprocessor part for data transmission and reception by holding transmit and receive data, transmit and receive addresses, and a write/read indication signal stable in the instruction cycle of a transmission/reception part. CONSTITUTION:The microprocessor part 6 sets up and outputs transmit data and a transmission and reception part address onto a data bus 37 and an address line 39 during transmission and holds a W-command signal at a high level. Then, significant data on the bus 37 is latched in a data latch circuit 25 by a clock. Similarly, the address signal and W-command and R-command sigals are also latched respectively. When a signal is supplied to a terminal of the circuit 25 for determining a data transmission direction, the latched significant data is sent to the transmission/reception part 8 through the line 39.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention improves the processing capacity of a high-speed microprocessor by shortening the time occupied by data transmission and reception processing in a multi-line high-speed communication control device that accommodates multiple lines. The present invention relates to a control device for controlling the

FIG. 1 shows an example of a schematic configuration of a general multi-line high-speed communication system.

1 is a central processing unit (CPU), 2 is a multi-line high-speed communication control device, 3 is a communication line, 4 is a modem (MDM) 5
．． Reference numerals 6, 7, and 8 denote a CPU interface section, a high-speed microprocessor section, a transfer control section, and a transmitting/receiving section, which constitute the multi-line high-speed communication control device 2, respectively.

A high-speed microprocessor section 6c is located between the CPU interface section 5 and the transmitter/receiver section 8, controls data transfer, etc. performed between the CPU 1 and the transmitter/receiver section 8 via the CPU interface section 5, and performs transfer/reception processing. The control unit 7 receives write and read commands from the high-speed microprocessor unit 6, and in the case of transmission, transfers the data read from the CPU 1 to the transmitting/receiving unit 8 in parallel, and in the case of receiving, transfers the data read from the transmitting/receiving unit to the CPU interface unit. 5 to perform the conversion.

Conventionally, the above-mentioned transfer control section 7 is
It consisted of a circuit as shown within the dashed line in the figure. In the figure, 9 is bidirectional data.

10 is an address line of the transmitter/receiver section 8, 11 to 19 are write/read control lines, 20 is a clock signal line, 21 is a timing circuit, 22 is an OR circuit, 23.
24 is an AND circuit. The operation of the transfer control section 7 is as follows.

In the case of data transmission from the high-speed microprocessor section 6 to the transmitting/receiving section 8, the high-speed microprocessor section 6 first determines the transmission data and the transmitting/receiving section address as shown in FIG. The valid transmission data and the effective address of the transmitting/receiving unit are sent to the transmitting/receiving unit 8 via the address line 1θ, and the write instruction signal (hereinafter referred to as W-command) is set to a high level as shown in FIG. 3(c). The signal on line 15 and the signal on line 16 (described later) are applied to lines 11 and 15, and the OR gate 22 performs an OR operation to set the output of the OR gate 22 to a high level.
A trigger is applied to the timing circuit 21 through the line 17, and the signal on the line 18 connected to the timing circuit 2 is set to high level by the clock signal of FIG. 3(a) applied to the timing circuit 2I through the line 20. 19
The signal on line 1 and line 18 are set to low level.
The write/write signal (hereinafter referred to as W-/e) shown in FIG.
Rus. ) to the transmitter/receiver section 8 via line 13.
, the write cycle of the transmitting/receiving section 8 begins.

Thereafter, during the write cycle, the high-speed micro 70 processor section 6 continues to validate data, addresses, and W-commands as shown in FIGS. 3(b) and 3(c).

A certain period of time set by the timey puffer circuit 2 (indicates from the start to the end of the write cycle of the transmitting/receiving section 8)
After the elapsed time, the output of the side connected to line 18 of timing circuit 2 becomes low level, the output of the side connected to line 19 becomes high level, and the signal on line 18 and the signal on line 11 become logical at AND/DART 23. After the product operation is performed, the output of the AND gate 23 becomes low level, which notifies the transmitter/receiver section 8 of the end of writing via the line 13, and sends the instruction end pulse of FIG. 3(e) to the high-speed microprocessor section 6 via the line 19. is sent to signal the end of the write cycle.

In addition, in the case of reception in which the high-speed microprocessor 6 receives data sent from the transmitting/receiving section 8, the high-speed microprocessor 6 first determines the receiving section address as shown in FIG. The effective address of the transmitting/receiving unit is sent to the transmitting/receiving unit 8 via the line 1θ, and
) as a read instruction signal (hereinafter referred to as R-command).
to high level and connect this signal to line 12. Further, the signal on line 16 and the signal on line 15 described above are ORed together in OR gate 22, and OR gate 22 is applied.
The output of the timing circuit 2 is set to a high level, and a trigger is applied to the timing circuit 2 through the line 17, and the clock signal shown in FIG. The signal on the connected line 18 is set to high level, the signal on line 19 is set to low level, and the signal on line 12 and line 18 is set to AND gate 2.
The read pulse signal (hereinafter referred to as "R-pulse") shown in FIG. 3(d) obtained by performing the AND operation in accordance with 4 is sent to the transmitter/receiver section 8 via the line 14, and a read cycle of the transmitter/receiver section 8 begins.

Thereafter, during the read cycle, the high speed microprocessor 6 continues to enable the address and R-command as shown in FIGS. 3(b) and 3(c).

After a certain period of time set by the timing circuit 2 (indicating from the start to the end of the read cycle of the transmitting/receiving section 8) has elapsed, the output of the timing circuit 21 connected to the line 8 is connected to the low level line 19. The signal on line 18 whose output is high level and the signal on line 12 are ANDed by AND gate 24, and the output of AND gate 24 becomes low level. The transmission/reception unit 8 is notified of the end of reading, and the instruction end/reception shown in FIG.
Valid data is sampled to signal the end of the read cycle.

When the transfer control section 7 uses a circuit as described above, the writing and reading cycles of the transmitting/receiving section 8 are performed once by the high-speed microprocessor section 6.

between write and read cycles, which is slower than the processing time of
Since the data address and W-command/R-command must be kept valid, the high-speed microprocessor unit 6 has to be in a waiting state during the write and read cycles as shown in FIG. 3(f). The invention was made in view of this point, and during the write and read cycles of the transmitting/receiving section 8, the data is stored.

By providing a circuit that holds the address, W-command/R-command signals, and a circuit that controls them, the above-mentioned drawbacks are eliminated, the waiting time of the high-speed microprocessor section 6 is eliminated, and the processing capacity of the high-speed microprocessor section 6 is improved. This is an attempt to improve the situation.

The present invention will be described in detail below with reference to the drawings.

FIG. 4 is a circuit diagram showing one embodiment of the present invention, and FIGS. 5 and 6 are time charts for explaining its operation. In this figure, the same components as in FIGS. 1 to 3 are given the same reference numerals.

In FIG. 4, 25 is a bidirectional data latch circuit 26 is an address latch circuit, 27 is a flip-flop (hereinafter referred to as W-FF) that holds the above-mentioned W-command,
28 is a flip-flop (hereinafter referred to as R-FF) that holds the above-mentioned R-command, and 29 is a flip-flop (hereinafter referred to as R-FF) for notifying the high-speed microprocessor 6 of the end of the read cycle of the transmitter/receiver 8. (This is the instruction end FF.)

Next, the operation of the transfer control section 7 configured as described above will be explained using FIGS. 4, 5, and 6.

At the time of transmission, the high-speed microprocessor section 6 first determines the transmission data and the transmitter/receiver address, and then transfers the data bus 37. It outputs on address line 39, sets the W-command signal to high level, and connects W-FF 27. via line 4. and·
Kate 30. Or dirt 31.33 Figure 5 (b)
Give like. A high level W-command signal is transmitted through line 4, as shown in FIG. 5(b), and a clock signal of FIG. 5(a) is transmitted through line 20, as shown in FIG.
This is a terminal (hereinafter referred to as a strobe terminal) that performs an AND operation in the AND gate 30 and samples the data of the data latch circuit 25 via the line 43.
Valid data on the bidirectional bus 37 is shown in FIG.
The data is latched by the data latch circuit 25 as shown in c).

Also, when a high level W-command signal is applied to the set input terminal of the W-FF 27 via the line 41, the signal shown in FIG.
As in e), the output of the W-FF 27 becomes high level. (
, at this time the reset input connected to line 52 of W-FF 27 remains at a low level. ) Also, a high level W-command signal is applied to the OR gate 3'3 via line 4, and is logically summed together with a low level R-command signal (described later) by the OR gate 33. A high level signal is applied to one side of AND gate 34 via line 46, and is ANDed in AND gate 34 with a clock signal applied to the other side of AND gate 34 via line 2o. Address latch circuit 2
6 and the effective address on line 39 is shown in FIG.
The valid address is latched by the address latch circuit 26 as shown in c) and sent to the transmitter/receiver section 8 via the line 40.

Furthermore, the high level output signal of the W-FF 27 is sent to the OR gate 3 via line 48.

35, 771'・ke” - Humiliated by 23, or
In dart 3, it is logically summed together with the high level W-command signal applied via line 4 and sent via line 44 to a terminal that determines the data sending direction of data latch circuit 25 (see FIG. 5). A high level signal is applied as shown in d), and the valid data latched in the data latch circuit described above is sent to the transmitting/receiving section 8 via the line 38. Also, in the OR gate 35, it is ORed together with a low level R-FF signal applied via a line 49, which will be described later, and a high level signal is applied to the timing circuit 21 via a line 50. 20 to the timing circuit 2, the output of the timing circuit 21 connected to the line 5I becomes high level as shown in FIG. 5(f). The output of the connected side remains at a low level. ) through line 5 no and ke”
- This high level signal is applied to one of the gates 23, and together with the high level signal on the aforementioned line 48, the AND gate 23
A logical AND operation is performed on the signals, and a high-level W-7N pulse signal is applied to the transmitting/receiving section 8 via the line 13 as shown in FIG. 5(f).

In the above state, the valid data latched by the data latch circuit 25 is on the bidirectional path 38, the valid address latched by the address latch circuit 26 is on the address line 40, and the w-FF27/'i A high level signal indicating a write instruction, a low level signal for R-FF 28, a high level signal indicating that the transmitter/receiver 8 is in a write cycle on line 5, a high level signal indicating a write instruction on line 13, A low level signal is output on I4.

When the write cycle of the transmitting/receiving section 8 is completed, the output of the timing circuit 2 connected to the line 5 becomes low level as shown in FIG. 5(f), and the output of the AND gate 23 becomes the low level as shown in FIG. It becomes a low level.

Further, when the output of the timing circuit 21 connected to the line 52 is at a high level as shown in FIG. becomes a low level as shown in FIG. 5(e), the output of the timing circuit 21 connected to the line 52 becomes a low level, and the 91st write cycle is completed.

The waiting time of the high-speed microprocessor section 6 during the above transmission is between the high levels shown in FIG. 5(h).

At the time of reception, the high-speed microphone resetter section 6 first determines the transmitting/receiving address, outputs it on the address line 39, sets the R-command signal to high level, and sends the Ft-FF2B and OR-K via the line 42. Figure 6(b) in 33
Give like.

A high level R-command signal is transmitted via line 42 to the R-
When applied to the set input terminal of FF2B, Fig. 6(f)
The output of R-FF28 becomes high level. (At this time, the set input connected to line 52 of R-FF 28 remains at a low level.) Also, a high level R-command signal is provided to OR gate 33 via line 42. It is logically ORed with the aforementioned low level W-command signal in the OR gate 33, and a high level signal is applied to one of the AND gates 34 via line 46, and the other of the AND gates 34 is given a high level signal. The AND gate 34 performs an AND operation with the clock signal shown in FIG. 6 (,) applied through the line 20, and the result is applied to the address latch circuit 26 through the line 47. ) is input to the address latch circuit 26, and the valid address is sent to the transceiver section 8 via line 40.

Additionally, the high level output signal of R-FF 28 is routed through line 49 to ORGOUT 35.AND 8-24.3.
6, which is logically ORed in gate 35 with the low level W-FF signal provided via line 48, and a high level signal is sent via line 50 to timing circuit 2. 6(a) which is applied to the timing circuit 2 via line 20, the output of the timing circuit 21 connected to line 51 becomes high level as shown in FIG. 6(g). (At this time, the output of the side connected to line 52 of timing circuit 21 is low level it.) This high level signal is applied to one side of AND dart 24 via line 5, and the above-mentioned line The AND gate 24 performs a logical AND operation with the high level signal of 49, and the high level R-.Grus signal is sent to the transmitter/receiver section 8 via the line 14 as shown in FIG. 6(g).
It is given as follows.

In the above state, undefined data is on the bidirectional path 38, a valid address latched by the address latch circuit 26 is on the address line 40, and R-FF2. !
i is a high level signal indicating a read instruction, W-FF 27 is a low level signal, line 5 is a high level signal indicating that the transmitter/receiver 8 is in the read cycle, and line 14 is a high level signal indicating a continuous read instruction. , a low level signal is output on line 13.

When the read cycle of the transmitter/receiver 8 is completed, the line 51
The output of the timing circuit 21 connected to is shown in FIG. 6(g).
It is a low level like , and furthermore, and
The output of No. 4 becomes a low level as shown in FIG. 6(g).

Also, the output of the timing circuit 2 connected to the line 52 becomes high level as shown in FIG.
32 and via line 20.
) The valid data sent from the transmitter/receiver section 8 is logically ANDed by the AND gate 32 together with the black and red signals inputted to the input terminal 32, and is applied to the strobe terminal of the data latch circuit 25 via the line 45. The data is latched by the data latch circuit 25 as shown in FIG. Or dirt 3 and 41 life low level W-command signal trine 4
The low level W-FF signals of 8 are logically ORed, and the low level signal of FIG.
Valid data applied to the terminal for determining the data output of the latch circuit 25 and latched by the data latch circuit 25 described above is applied to the high-speed microprocessor section 6 via the bidirectional path 37.

Further, the high level signal shown in FIG. 6(h) is applied to the reset terminal of R-FF2B via line 52, and the output of R-FF2B becomes low level as shown in FIG. 6(f), and line 49.
Anne]・0・Gate 35. The output of the side of the timing circuit 21 connected to the line 52 via the line 50 becomes low level as shown in FIG. 6(h). Further, the AND gate 36 performs an AND operation on the high level signal on the line 52 and the high level signal on the line 49, and a high level signal is applied to the set input port of the instruction end FF 29 via the line 53. The output of the instruction end FF 29 becomes high level as shown in FIG. When the received valid data on the line 37 is sampled as shown in FIG. 6(e), a high level reset signal is applied to the reset input of the instruction end FF 29 via the line 55 as shown in FIG. 6(j), and the instruction end FF 29 is reset. The output is shown in Figure 6 (
As in 1), one read cycle is completed at a low level. The waiting time of the high-speed microprocessor section 6 during the above reception is between the high levels shown in FIG. 6(k).

As described in detail above, according to the present invention, by keeping the transmitted/received data, the transmitted/received address, and the write/read instruction signal stable during the instruction cycle of the transmitting/receiving section, data transmission/reception of the high-speed microprocessor section is stopped. Therefore, it becomes possible to easily increase the processing capacity of the high-speed microprocessor section.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the schematic configuration of a general multi-line high-speed communication system, Fig. 2 is a circuit diagram showing the transfer control section of Fig. 1, and Fig. 3 is an explanation of the operation of Fig. 2. FIG. 4 is a circuit diagram of a transfer control section showing one embodiment of the present invention, and FIGS. 5 and 6 are time charts for explaining the operation of FIG. 4. 25...Bidirectional latch, 26...Latch, 27°28.29...Flip-flop. Patent applicant Oki Electric Industry Co., Ltd. Figure 3 (f) Figure 6 Figure 15 (0) (j) (k) -L''-

Claims (1)

[Claims] In a multi-line high-speed communication control device in which a plurality of communication lines are controlled by a high-speed microprocessor via a transmitting/receiving unit, at least during a transmission cycle, the microprocessor sends a data signal to the transmitting/receiving unit, a transmitting/receiving unit address signal, and a transmitting/receiving unit address signal. a circuit that holds a signal indicating the request state and clears the signal indicating the request state at the end of a transmission cycle; and a transmitting/receiving section address signal and receiving request state that the microprocessor sends to the transmitting/receiving section at least during the receiving cycle. a circuit that holds a signal indicating the receiving cycle, holds a data signal that the transmitter/receiver sends to the microprocessor at the end of the receiving cycle, clears a signal indicating the receiving request state, and notifies the microprocessor of the end of the receiving cycle; A multi-line high-speed communication control device, characterized in that it is provided between a processor and the transmitter/receiver.