JPS5971165A - Rotation control system of recording disc - Google Patents

Abstract

PURPOSE:To bring the disc rotation quickly from the standstill to the vicinity of the specified line speed and to attain ease of reproducing clock extraction afterward, by applying at first rotation acceleration at disc start to drive the disc near the specified speed and then switching the control to the frame synchronism servo. CONSTITUTION:The recording disc is accelerated once by applying a prescribed voltage (or current) to a motor for a prescribed time in response to a rotation start command. A reproduced RF signal from a pickup 2 is shaped at a waveform shaping device 3 to obtain an EMF signal. This signal is inputted to a frame synchronism servo device 4 and a frame synchronism servo signal is generated. This servo signal is impressed to a spindle drive device 6 via a switching device 5 to apply the SYNC servo to the spindle motor. Since a constant voltage +V is impressed to the spindle drive device 6 via a low resistance Ro1, a large constant current (or constant voltage) is applied to the spindle motor in case of the ACC operation of the accelerating function. In case of HDL operation, a small constant current (or constant voltage) is applied to the spindle motor so that the value of resistor R02 is selected larger then the value of resister R01 and the HLD operation is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a recording disk rotation control system, and more particularly to a recording disk rotation servo system for controlling the rotation of a disk on which digital signals are recorded.

2. Description of the Related Art In recent years, research has been carried out on techniques for converting analog information such as audio signals into PCM (pulse code modulation) and recording them in a digital signal format of 1 or 0 on a recording medium, and this technology is being put into practical use. In this case, in order to facilitate demodulation of the digital signal, a so-called self-clocking modulation method is used, and in order to achieve higher density recording, instead of a rotational angular velocity constant force method,
Constant linear velocity where the linear velocity of all recording tracks is constant (
CLV) format. Such CLV
When playing a disc, it is necessary to control the rotation of the disc so that it maintains a constant linear velocity, and for this purpose, reproduced clock information of a predetermined frequency is extracted from the reproduced signal and based on this clock signal. It is common to form a spindle servo.

An example of this modulation method is EFM (Eight 1:
.

Fourteen Modulation) system, which has a format as shown in FIG. For example, one frame consists of 588 bits, and the data signal is converted to 14 bits every 8 bits using the EFM method according to a predetermined conversion table (not shown), and 3 adjustment bits are added to make 17 bits. is one unit, and when it is 1, there is an inversion from logic H level to logic L level or vice versa, and when it is 0, there is no inversion, that is, NR,
It is recorded in the form of 7I.

At the beginning of each frame, a frame sync signal is set such that the first bit is 1, the second to 11th bits are 01, the 12th bit is 1, the 13th to 22nd bits are 01, and the 23rd bit is 1. recorded. A control signal is placed at a predetermined position of 588 bits based on this frame sync signal.

Throughout the signal processing, signal processing is performed such that 2 or more and 10 or less O's are placed between 1's. That is, the minimum inversion interval of the signal level is 3T (T is the length of the bit cell), and the maximum inversion interval is 11T. Further, in parts other than the frame sync signal, the maximum inversion interval is prevented from occurring two or more times in succession.

A signal equivalent to a full-wave rectified version of this modulated signal is input into a PLL (phased-locked loop) to extract clock information and perform signal reproduction processing. In some cases, the musical tone data becomes a fixed pattern corresponding to the zero level. In this case, the EFM signal is inverted every 7T, 3T, and 7T, for example.
This is a time-series signal that includes many repetitive waveforms with one period of 17T. In addition to the spectrum of the clock information frequency (4,3218 MHz), the input signal of the PLL in the above-mentioned non-musical band part is a spectrum of 1 of the clock frequency from the bright line spectrum.
1/7 frequency <254. It has high energy level spurs at frequencies shifted by an integer multiple of K)-1z). Since the frequency of this spurious is close to that of the positive phase clock, it is difficult to distinguish between the two based on frequency. Therefore, the clock extraction PLL may mislock due to this large spurious energy level, making it impossible to accurately extract the lock and, further, to reproduce the data accurately. Furthermore, if the input signal frequency of the PLL is significantly deviated from the correct frequency, no lock can be achieved.

Therefore, when starting up, especially during the part of the music band, or when moving the pickup greatly and quickly in the radial direction of the disc to search for address information, etc.
The rotational speed of the disk may differ significantly from the specified speed, making it impossible to extract the correct clock.As a result, it is necessary to control the disk to the correct rotational speed so that the correct clock can be extracted again. The disadvantage is that it takes a long time.

The present invention was made in view of this situation, and its purpose is to provide a rotation control method that can quickly control a disk to a substantially accurate rotational speed of 5 - from a stopped state. That's true.

The disk rotation control method according to the present invention is a rotation control method for a recording disk on which a digital signal including a synchronization signal with a maximum interval of 0 consecutive reversals (n is an integer) is recorded, and the disk rotation control method includes predetermined constant voltage (or current)
The recording disk is accelerated once by supplying it to the motor for a predetermined period of time, and then a period of n times the maximum reversal interval included in the reproduction signal by the pickup is detected, and the detection signal is used to control the rotation of the disk. Features.

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 2 is a schematic block diagram of an embodiment of the present invention, mainly depicting a spindle control system for disk rotation control. Before explaining FIG. 2, the main operating functions of the spindle control system will be described. The first function is an acceleration function (<ACC function), which increases the motor rotation speed by flowing a large constant current to the spindle motor, and the second function is a holding function () ILD function). There it is,
Rotating system lli! by passing a small constant current through the spindle motor. This is to maintain a constant rotation speed against frictional force. The third function is the frame sync servo function (
SYNC servo function) is a function that detects frame sync directly from the reproduced RF signal (without extracting the reproduced clock) and controls the rotation speed so that a substantially accurate linear velocity is achieved. The fourth function is the quartz servo function (Q
RTZ servo function), which demodulates the EFM signal using the frequency error signal obtained by comparing the signal corresponding to the frequency of the reproduced clock signal extracted from the signal and the reference signal and the reproduced clock signal. Then, using the phase error signal obtained by comparing the phase of the frame sync detected from this demodulated signal and the phase of the reference frame sync (+-1 to 7, 35), the disk rotation speed is controlled and accurate. The purpose is to obtain linear velocity.

These four functions are 800, 1-ILD, and 5YNC from the system controller 1 (see Figure 2).

It operates selectively depending on each QRTZ control signal.

When the disk does not need to rotate (during stop and eject operations), none of these control signals are output, and the spindle motor drive current is set to zero.

Referring to FIG. 2, the reproduced RF signal from the pickup 2 is shaped by a waveform shaper 3 to become an EFM signal.

This signal is input to the frame sync servo device 4 and a frame sync servo signal is generated. This servo signal is applied to the spindle driver 6 via the switch 5, and the spindle motor is set to 5YNC servo.

In the case of ΔCC operation, constant voltage + is applied via low resistance Ro+.
is applied to the spindle driver 6, a large constant current (or constant voltage) is supplied to the spindle motor, resulting in ΔCC operation. Furthermore, in the case of HLD operation, the value of resistor R02 is selected to be as large as resistance Ro+ so that a small constant current (or constant voltage) is supplied to the spindle motor, thereby enabling HLD operation.

The output of the waveform shaper 3 is input to a clock extractor 7, and this extractor 7 has a PLL (phase locked loop) circuit configuration that locks to clock information of a predetermined frequency included in reproduction information. The reproduced clock signal extracted at this Pshishi 7 and the previous waveform shaping output are demodulated at 8
Both signals are input to the NRZ signal and converted into a predetermined digital signal (NRZ) signal. The demodulated output is input to a RAM (random access memory) 9 and read out using constant read clock pulses, and is converted into analog information by an A/A converter 10 and output as an audio output.

An error corrector 11 detects and corrects bit errors and burst errors, and the operations of the error corrector 11 and the RAM 9 are controlled by a RAM controller 12.

The demodulator 8 also has a sync detection function for detecting frame sync from the EFM signal using the reproduced clock, and the RAM controller 12 is controlled by the timing of occurrence of this reproduced frame sync. On the other hand, the frequency divider 1 of this playback frame sync
The frequency-divided output from the frequency divider 15 of the reference frame signal generated from the reference signal generator 14 is supplied to the other human inputs. The phase comparison output is level-adjusted in the level shifter 16 and then sent to the adder 17 as a phase error signal.
It becomes human power.

The output of the level shifter 18 which compares the output of the loop filter (see 73 in FIG. 5) in the PLL 7 with a predetermined reference voltage and adjusts the level of the comparison output is sent to the adder 17 as a frequency error signal. The output of the adder 17 is applied as a quartz servo signal to the spindle driver 6. Further, the frame sync detection output of the demodulator 8 is supplied to the system controller 1. This detection output controls the state of the switch 5 and switches the spindle servo operation, which will be described in detail later. Furthermore, the system controller 1 supplies a control signal for sweeping or forced sweeping the oscillation frequency of CO10- (see 74 in FIG. 5) of the PLL 7, or a forced sweep control signal. will also be described later.

Note that 19 indicates a keyboard, which means an operation panel or a remote control board of the playback device. 20 and 2
Reference numeral 1 indicates a tracking servo system and a focus servo system, the operations of which are also controlled by a system controller 1.

FIG. 3 is a block diagram showing a specific example of the frame sync servo device 4, and the reproduced EFM signal as shown in FIG.
The signal is input to retriggerable MMV (monostable multivibrator) 41 and 42 . It is assumed that the MMV 41 is triggered when the input signal is reversed in the positive direction, and the MMV 42 is triggered when the input signal is reversed in the negative direction, and each outputs a logic signal of To for a certain period of time. The outputs of both MMVs become trigger inputs of the retriggerable MMV 44 via the OR gate 43, and this MMV/! The output of I4 is converted to a DC level by LPF45. This DC level is determined by comparator 4.
6, the level is compared with a reference level 47, and the comparison output becomes a sync servo signal, which is input to the switch 5 shown in FIG. Note that a reset signal is supplied to the MMV-14 and LPF 45 from the outside, and when the sink servo is off, the timing of this reset signal discharges the capacitor of the time constant circuit of the MMV 44 and LPF 45, returning to the initial state. It looks like this.

Therefore, the settling time when the sync servo is next turned on is shortened.

Here, the output pulse width T of MMV41.42.

is the period of the frame synchronization signal (twice the maximum inversion interval) 2
It is set approximately equal to 2T (strictly speaking, it is 20 to 30 ns shorter than 22T). Also, the output pulse width T1 of MMV44 is the cycle of the frame synchronization signal (for example, 1/7.35
It is assumed that the frequency is set to be smaller than the KHz phrase (136 μs) (for example, 1/2 of the frame synchronization signal frequency). EFM
As shown in FIG. 1, it is not determined whether the frame sync of a signal starts from a rising edge or a falling edge, and this is due to the nature of the EFM signal. MMV4 is triggered by the rising and falling edges of the input signal, respectively.
1.42 is established.

Now, the only time the interval from one rising edge of the input signal to the next rising edge or from one falling edge to the next falling edge is 227 is in the case of frame sync, so if the disk rotates at the correct linear speed. If so, this 22T interval would be approximately 5.09μs, so
The output pulse width To of the retriggerable MMV41.42 is approximately 20 to 30 ns (next stage MMV
(width as a pulse that can trigger 44) is set short.

FIG. 4 shows an operation timing chart of the circuit in FIG. 3, where <A> is when the linear velocity exceeds the specified value;
(B) shows when it is approximately at the specified value, and (C) shows when it is smaller than the specified value. In other words, when the linear velocity is large as in (A), the next rising edge always arrives before 5.09 μs has elapsed from the input rising edge (the same applies to falling edges). Therefore, MMV41 continues to be triggered and its output maintains a low level. (B)
In a substantially proper case like this, the rising edge interval only in the frame sync portion is 5.09 μs, so a narrow pulse of about 20 to 3 Qns can be obtained at the output of the MMV 41 in synchronization with the frame sync. Next, when the linear velocity is small as shown in (C), pulses are obtained in the output of the MMV 41 in the frame sync portion and other portions as well.

In this way, since the number of output pulses of the OR gate 43 changes depending on the linear velocity, the MM
Trigger V44 to generate a pulse train of a predetermined width.
If the F45 performs DC conversion, an F/V converted signal of the reproduced signal will be obtained as the output of the LPF 45.

In other words, if the linear velocity of the disk is correct, MMV44 is triggered only in the frame sync part, so F/V
The conversion signal shows a predetermined value, but if it is faster than 14-1, the MMV471 will not be triggered and the F/■ conversion signal will be zero; if it is slower, the MMV44 will be triggered in the frame sync part and other parts, so the F/■ conversion signal will be zero. /V conversion signal becomes larger than the predetermined value. A servo signal is obtained by comparing the level of this F/V conversion output with a level 47 corresponding to one-line velocity.

By the way, how the output voltage of the LPF (45 in FIG. 3), which is an F/V converter, changes with respect to a change in the linear velocity of the disk will be explained with reference to FIG. 5.

If the disk is rotating faster than the correct linear velocity ``U'', the trigger pulse of MMV44 will not occur as shown in Figure 4 (A), so the output voltage will be zero. If the rotation is slightly R, a trigger pulse of MMV44 will occur at each frame sync frequency, so the output voltage will be at the frame sync frequency7.
This value corresponds to 35KHz. As the linear velocity gradually becomes slower than v22, the frame sync frequency itself also decreases to 7.
Since the output voltage decreases from 35 Kl-1z, the output voltage also decreases accordingly. However, when the linear velocity becomes V21, which is about 4.5% slower than the correct linear velocity V22,
Since 21T has a time width (5.09 μs) equivalent to 227, in addition to frame sync where the transition interval is 22T, MMV44 can also be used at the transition interval of 21T included in the signal.
trigger pulse occurs, so that the output voltage increases suddenly. A similar change occurs as the linear velocity gradually decreases. Also, when the linear velocity becomes very slow, M
Since the next trigger pulse arrives between the time the MV 44 is triggered and the end of the output pulse, the MMV 44 continues to be triggered, and thus the output voltage saturates to its maximum value.

In this way, the difference signal between the LPF output voltage and level 47, which has the characteristics shown in Fig. 5, is used as a servo signal, but level 47 corresponds to the correct frame sync frequency of 7.35 KHz. value (predetermined value a in Figure 5), the output voltage of the LPF will be V2+ and 1f in addition to 1J22.
Since it is equal to the predetermined value a even at a linear velocity of 20 mag.
There are many stable points, making it impossible to operate the servo correctly. However, if level 47 is set to 7.3 as shown in b in Figure 5,
If the value is set sufficiently lower (for example, about half) than the value corresponding to 5Kl-12, there will be only one stable point at the correct linear velocity 'U, and therefore almost accurate linear velocity knurling can be performed.

That is, the circuit system shown in FIG. 3 detects a period n times the maximum inversion interval of the reproduced signal (n=2 in the embodiment) by comparing it with a reference period, and generates a signal corresponding to this detection signal, that is, F/ A frame sync servo signal is obtained by generating a V conversion signal and comparing this signal with a reference value.

By driving the spindle motor using this servo signal, the recording disk can be driven at a substantially accurate linear velocity. This frame sync servo is extremely useful when clock information cannot be extracted from the reproduced signal, such as during startup or search (search for address information) operations.

Next, details of the quartz servo function will be explained. Digital information that is reproduced from a recording disk that is rotating while having wow and flutter is once stored in the RAM 9.
(See FIG. 2), is read out using a constant clock signal and subjected to D/A conversion, resulting in a high quality audio signal without wow and flutter. in this case,
Due to the limited capacity of RAM, if the reading and writing speeds are not exactly equal on average, the stored information in the RAM will be empty or vice versa.

In this case, the reproduced sound becomes choppy.

Therefore, when reproducing musical tone signals, the quartz servo is operated to maintain the disk linear velocity constant and to always match the writing speed with the reading speed. That is,
The phase comparator 14 compares the phases of the frequency-divided output of the reproduced frame sync and the frequency-divided output of the reference frame sync signal obtained from the demodulator 8 in FIG. (may also be directly compared), and a signal corresponding to this phase difference is applied to the spindle motor after being combined with the servo signal.

However, since this phase error alone does not provide adequate damping characteristics for a servo, it is necessary to further introduce a frequency error and mix it with the phase error.

Therefore, since the 1-1) F output voltage of the clock extraction PLL 7 corresponds to the frequency of the reproduced clock signal, this voltage is compared with the base tP- voltage and the comparison output is used as frequency error information to adder 17. The quartz servo signal is obtained by adding it to the phase error information. By applying this quartz servo, it becomes possible to perform accurate linear velocity servo in which the reading and writing speeds of the RAM 9 are exactly equal on average. Therefore, at startup, acceleration (ACC > operation) followed by holding (ILD > operation) is performed in order to bring the rotational speed of the spindle motor to a certain level, and after that, even if no clock signal is extracted, the speed is close to the specified linear velocity to some extent. Frame sync with speed control (
SYNC) Servo operation.

Thereafter, after confirming that the playback frame sync has been detected, the system switches to quartz servo (QRTZ) servo operation to maintain a constant prescribed linear velocity.

FIG. 6 is a block diagram of the PLL 7 for extracting self-clock information from the reproduced EFM signal.
) is input to the edge detector 71, and a pulse (B) synchronized with the level transition timing of the reproduced signal (Δ) is generated. This edge pulse (B) is set to have a pulse width approximately equal to a half period of the clock signal for normal vision. This edge pulse becomes the single power of the phase comparator 72,
(2) The phase is compared with the output (C) of C074. This phase difference output is converted into a direct current by the LPF 73 and becomes a control signal for the vCO 74. The output of this VCO 74 is pulsed by a waveform shaper 75 and output as a reproduced clock signal. In addition, in order to quickly lock the PLL, use LPF73.
Sweep control is performed using the output of the VCO 74, and the sweep controller 76 controls the oscillation frequency of the VCO 74 to sweep between a predetermined upper limit and lower limit. Also, P
A forced sweep control signal is sent to the sweep controller 7 in order to apply a disturbance to the PLL 7 to release the LL mislock and perform a forced sweep faster than the previous sweep operation.
6, and these sweep control and forced sweep control are performed by commands from the system controller 1 shown in FIG.

FIG. 7 is the operating waveform of PLL7 in FIG. 6, and (A)
.about.(C) correspond to the waveforms of the signals (Δ) to (C) of the blocks in FIG. As you can see from the diagram, VCO74
The output is 4.3218MHz at normal linear speed.
A sine wave of (bright line spectrum component) is obtained, and clock extraction becomes possible.

FIG. 8 is a circuit diagram of the frame sync detector included in the demodulator 8 of FIG.
1 input, and a pulse responsive to the level transition timing of the reproduced signal is generated.

This edge pulse is operated by a regenerated clock signal.
The data are sequentially written into the 3-bit shift register 82. A total of 10 bits output from the 2nd bit to the 21st bit to the 11th bit of this shift register 82 is output from the Nant gate 83.
The total 10-bit output from the 13th bit to the 22nd bit of the shift register is the input to the Nant gate 84.

The outputs of both Nand gates and the outputs of the 1st, 12th, and 23rd bits of the shift register 82 are input to a 5-person NAND gate 85, and the output of this gate serves as a reset signal for the counter 86. There is. The counter receives the reproduced clock as an input, and the output of this counter is derived as a frame sync detection signal and supplied to the system controller 1.

When a frame sync signal is included in the reproduced EFM signal and this frame sync signal has been input,
The contents of the shift register 82 are as shown in the figure. Therefore, the output of the AND gate 85 at this point indicates a logic H (1) level, and is logic (0) in all other cases.
It will show your level. Therefore, if the counter 86 is set to correspond to one frame of the reproduced signal, that is, a 588-bit counter 22-, the counter 86 is always reset to zero at the end of frame sync, so the frame sync detection signal indicates that the reproduced frame sync is detected. When it is, it is derived as a logic 1-level. On the other hand, when the counter 86 counts 588 reproduced clocks, if no frame sync arrives, the counter 86 is not reset and outputs a logic H signal. (Whether or not the correct reproduced clock has been extracted) can be identified.

Switching from frame sync servo to quartz servo is performed only when this playback frame sync is detected, and if playback frame sync is not detected during frame sync servo, switching to quartz servo is not possible. Since this is impossible, PLL7 is forcibly swept to control the forced pull-in to clock information.

FIG. 9 is a diagram showing a specific example of the sweep restrictor 76 shown in FIG. 6. In both figures, the same parts are designated by the same reference numerals and the explanation thereof will be omitted. DC voltages Vo and yh having different levels are applied to the anti-phase input of the amplifier OP1 constituting the loop filter 73 via switches 701 and 702, respectively, and further via resistors R3 and R4. Note that the filter 73 includes a resistor R+ in addition to an amplifier OP+ and a capacitor C+.

It has an active filter configuration with R2.

For control of switches 701 and 702, R-S flip 70 knob 70 consisting of three-person gate G+, G2
3 is provided, and the switch 701 is turned on and off by the output (C) of the gate G1, and the switch 702 is turned on and off by the output (D) of the gate G2.

Furthermore, the output of the loop filter 73 (T1), that is, the VCO
Level comparators 704, 705 are provided to determine the upper and lower limits of the control input voltage level of 74. A voltage Vm that determines the upper limit level is applied to the negative phase input of one comparator 704, and a voltage Vn that determines the lower limit level is applied to the positive phase input of the other comparator 705. Both comparators 704,
The output (G1) of L P F 73 is supplied to the positive phase and negative phase inputs of 705 . And both comparators 704. ,7
The outputs (I) and (J) of 05 are each flip-flop 70.
3 gates G2 and G1 are operated by one person and are used as set and reset inputs. A sweep control signal (A) is applied to the remaining inputs of gates G+ and G2 to perform sweep control.

A switch 706 is provided at both ends of the resistor R4.
It is turned on by the forced sweep control signal (B) and the resistance R
4 is shorted.

FIG. 10 is a diagram showing the operation of the circuit in FIG. 9, and (A)
. . . . . . . . . . . . . . . . . . . . . . . .(J). In addition, (E) and (F)
is a chart showing the on/off timing of the switches 701 and 702, and (G) is a chart showing the on/off timing of the switches 701 and 702.
This is a waveform showing the charging/discharging current. Sweep control signal (A
) is at the torque level, the flip-flop 703 is clamped to the reset state and no sweep operation occurs. When the signal (A) reaches the torque level, the 25-flip-flop 703 is released from the reset state and becomes capable of sweeping. Now, forced sweep control signal (B)
Assume that the switch 706 is turned off as the signal is at H level. When the switch 701 is turned on at this time, a charging/discharging current shown by (G) flows to the capacitor CI, and the LPF 73
The output gradually decreases as (1-1). When this output level reaches the lower limit level Vn (4V), the comparator 705 generates an output as shown in (J) to set the flip-flop 703. Therefore, the output of the flip-flop 703 is inverted as shown in (C) and (D), and the switch 701 is turned off and the switch 7o2 is turned on, so that the negative voltage vh
is applied to the capacitor C1, and the capacitor CI is discharged as shown in (G). By this, LPF7
The output of No. 3 gradually increases from the lower limit level Vn to the upper limit level Vm (6 V) as shown in (H).

When the upper limit level Vm is reached, the comparator 704 operates and resets the flip-flop 703, so the switch 70
The on/off states of 1 and 702 are reversed 26, and the LPF output (1'') changes again from the upper limit to the lower limit. In this way, a so-called sweep operation is performed in which the oscillation output frequency of the VCO 74 repeatedly increases and decreases within a certain range. For example, 4.3218MHz±200 Kl-I
The Z range is swept for approximately 1 On+s. This sweep is relatively slow and is only a small disturbance to the PLL, so once the PLL locks to the -H recovered clock frequency, it will never lose lock again.

Furthermore, since the sweep range is ±200 KHz, which is inside the spurious interval (254 + -12), the PLL will not mislock to the spurious as long as the disk is rotating at the correct linear velocity.

When this PLL mislocks due to spurious causes such as during a search, and in order to release the mislock, the forced sweep control signal (B) becomes L level and the switch 706 is turned on. Therefore, the resistor R4 is short-circuited, and the charging/discharging current to the capacitor C+ becomes large, and the sweep speed becomes faster (for example, about 100 times that of the normal sweep). The timing chart of each part in this case is shown as a forced sweep at the right end of FIG. In other words, a large disturbance is applied to the PLL, and the PLL is no longer able to maintain lock, the mislock is released, and a forced sweep is started. This forced sweep signal (B) is
The time width (
For example, the system controller does not need to return to H for several tens of microseconds after turning on the forced sweep signal (B). After that, the sweep speed becomes normal. Then, the system controller again monitors the presence or absence of 71 norm sync, and if frame sync is still not detected after a predetermined period of time (for example, about 1 Qms, which is one sweep period in FIG. 9), it performs forced sweep again. By repeating such operations until frame sync is detected, the PLL can be correctly locked.

An example of a flowchart for operating the spindle motor from startup to a stable state at a normal linear velocity using the above configuration is shown in FIG. 11.12. The pickup laser diode (L
D) is activated.

After the time required for the diode to stabilize (approximately 200 S) is taken into consideration, the acceleration (ACC) operation of the spindle motor is started, and at the same time, the focus servo pull-in operation is also started. This ACC operation is performed for approximately 500 m5 times, and then a hold (to ILD) is performed to maintain the rotation speed approximately constant.
It becomes an action. The focus servo locks at the earliest after the focus servo pull-in command is issued.
Since this is after 0IIIS (this 100m5 is the period during which the focus lens approaches the disk from the farthest position), the disk rotation speed increases to some extent due to the ACC operation during this period, and after 50011S, it reaches about 500 rpm. The rotation speed is reached. This is the track radius of the innermost circumference of the disk (approximately 241 m
) position (the pickup is always at this radial position during start-up), which is close to the rotational speed at which a constant linear velocity M is obtained.

During the 11L D operation after the ACC operation, the focus servo lock state is detected, but since activation is always performed at the position where the track exists, this detection is not performed in the playback R.
This is done by detecting the level of the F signal. Here, if the focus servo is not locked, the tracking servo cannot operate and the reproduction clock cannot be extracted, so the focus servo loop is opened and the focus servo pull-in operation is repeated again.

If the focus cannot be pulled even after two attempts, it will be ejected as unable to start.

If the focus servo is locked, the tracking servo loop is then turned on, and after a certain period of time (after the lock is stabilized), the frame sync (SYNC) servo operation is switched to. The demodulator 8 determines whether or not a playback frame sync is detected during the 5YNC servo. Even though frame sync is not detected, the disk rotation speed still deviates significantly from the correct value (approximately 30% to more than ±4.6%, which is the PLL sweep range of 4,3218MHz). Although the servo is in a state that substantially matches the range of ±200 KHz, or there is a spurious mislock, it is naturally impossible to shift to the quartz servo.

Therefore, the RF multiplier signal is checked again (this is to check whether the focus is out of focus due to strong external vibrations, etc.) to check whether or not the focus servo is locked. If the lock is released, it becomes stop mode. If the reproduced RF signal is good, forced sweep control of the PLL (as shown in FIG. 8) is performed, and as described above, for example,
After m5 elapses, it is determined again whether or not frame sync is detected.

That is, since frame sync is detected when PLI- is locked to the reproduced clock information, this forced sweep control operation is repeated until then. For example, if frame sync cannot be detected even after repeating this loop a predetermined number of times, the process shifts to eject mode. This is to take into consideration cases where the disc is extremely dirty, or the disc is installed upside down and crooked. When frame sync is detected, the system switches to quartz servo for the first time, and thereafter operates at a constant linear velocity.

As mentioned above, the reason why it is impossible to detect frame sync even if the reproduced RF signal is good after the frame sync servo is turned on is because the linear velocity becomes correct instantly after the frame sync servo is turned on. This is because it takes a certain amount of time due to the moment of inertia, etc., and the reason why the timing is not simply set until then is to extract the clock as quickly as possible.

Next, operation control of the spindle servo during a so-called search operation in which desired information is reproduced by searching for address information will be explained. This address information is 1
One bit is recorded at a specific location in a frame, and one address unit consists of 98 frames, ie, 98 bits. The last 16 bits of 98 bits are C.
RC (Cyclic Redundancy Ch)
eck) code, and is designed to enable error detection.

At the time of search, a target search address is specified, and the addresses are compared while performing a fast forward operation (slider control) of the relative position in the disk radial direction between the recording disk and the pickup information detection point. More specifically, the process repeats a few fast-forward operations, stops them, applies tracking servo, extracts the reproduced clock, reads address information, and compares it with the search address. Therefore, in order to shorten the search operation, it is desirable that the time required to stop fast forwarding and make the address information readable be as short as possible. On the other hand, during fast forwarding, the pickup crosses tracks one after another and the RF signal waveform is very disturbed, so the servo signal of the frame sync servo also has a large error, so it is not a good idea to apply the sync servo. Therefore, during feeding, the sink servo is turned off to maintain the rotation speed (
Switch to HLD > operation.

33- After fast forwarding a predetermined distance, it is necessary to read the address information and compare it with the search address, but this address reading period is controlled to a predetermined linear velocity or a speed close to it due to the need to extract the recovered clock. The need arises. Therefore, during this period, the frame sync servo operation is switched. That is, while performing the HLD operation, fast-forwarding a predetermined distance is performed to approach the search address, the HLD operation is turned off, and then the frame sync servo operation is switched to read and compare the addresses.

Here, during fast forwarding, the error of the frame sync servo becomes large as described above, and therefore, during this time, this large error voltage is applied to the capacitors such as the LPF 45 in FIG. 3. In this case, a large current will be supplied to the spindle motor when fast forwarding is stopped and switched to frame sync servo operation, and correct servo operation will be performed after the linear velocity has once deviated greatly. Therefore, it takes a long time until the clock extraction PLL 7 locks again, which causes a long search operation. Therefore, in order to prevent this drawback, when the sync servo is off, the system controller 1 generates a reset signal to discharge the capacitor of the frame sync servo system shown in FIG. 3.

FIG. 13 shows an example of a search operation, and shows a case where the search is started from an address portion smaller than the target search address. to-,-jl
The period is forward fast forward operation (FAST FW[)1)
During this period, the disk moves a predetermined distance in the radial direction while being maintained at a constant rotational speed by the l-ILO operation. During j+"tz, the address is read and compared with the search address while performing sync servo operation. Since the search address is larger, between t2 and t13) -
FAST FWDl is performed again while performing ILD operation, and address comparison is performed while performing sync servo operation from t3 to t4. At this time, the search address has been exceeded, so during the next period from 14 to t5, fast forwarding in the reverse direction (FAST RVS) of a predetermined distance is performed while performing HLD operation, and from t5 to t5.
6, addresses are compared by sync servo operation.

Since it is smaller than the search address, t6
- t7, the 1-ILD operation is performed, and the above type or reverse fast forward operation (FAST FWDl or FAST
RVS) FAST sends a shorter predetermined distance pickup
FWD2 operation is assumed.

Between 17 and t8, the addresses are compared using the sync servo, and when it is detected that the search address has been exceeded, the next fast forward operation is stopped and a so-called jump operation is performed using a tracking mirror or the like. That is, the rotation angle of the tracking mirror is changed instantaneously to cause the spot light, which is the information detection point, to jump over the adjacent one to easy. This jumping motion is divided into two stages. First, between 18 and t9, jump reverse (adjacent 1 to t9 in the opposite direction)
After repeating several to several dozen tracks (this is called a multi-jump reverse),
Perform address comparison. The jump operation for one track is performed instantaneously (about 100 to 500 μs). Therefore, the time during which the reproduced signal is disturbed is also within that range. Therefore, as mentioned above, a jump of several to several 10 tracks can be changed to, for example, several 1
If it is performed at intervals of 11S, the reproduced signal will be several I
The waveform is disturbed by several hundred microseconds for each IS, and with this degree of disturbance, it is sufficiently possible to control the linear velocity by the sync servo. Therefore, during multi-jump reverse, disk rotation is controlled by the sync servo. Perform margoo jump reverse and t9~t to
When it is found that the search address has been exceeded, the address is compared between t10 and t10. Do it until you reach it. Of course, rotation control is performed by the sync servo during the jump forward period as well. After reaching the search address at t11, the PLAY mode is set to finger 1.
If the mode is specified, normal playback will be performed using quartz servo, and if the PAUSE mode is specified, pause operation will be performed. The pause action is a repetition of a jump-reverse action of one track at the search point. During the pause operation, the playback signal is only disturbed by several 100 μs, which is the time of one jump, every several 100 m5, which is the time of one rotation. Therefore, the disk rotation control may be switched to quartz servo or may be left as sync servo.

Note that each step in FIG. 13 is repeated until the search address is exceeded.

The example shown in FIG. 13 is merely an example, and various modifications are possible.The point is that the hlLD operation is performed during slider feeding, and the frame sync servo operation is performed during address reading.

As described above, according to the present invention, when starting the disk, first the rotational acceleration operation is performed to drive the disk to a speed close to the specified speed,
Since the frame sync servo operation is then switched to, the disc rotation can be quickly brought from the stopped state to near the specified linear velocity, which has the advantage of making it easier to extract the reproduced clock from then on.

[Brief explanation of drawings]

Fig. 1 is a diagram showing a partial format example of EFM Shingetsu, Fig. 2 is a block diagram for an embodiment of the present invention, Fig. 3 is a block diagram of a frame sync servo circuit, and Fig. 4 is a diagram illustrating a frame sync servo circuit. is a block diagram of the frame sync servo circuit, Fig. 4 is a diagram explaining the operation of the circuit in Fig. 3, and Fig. 5 is a characteristic diagram of the Isamu frame sync servo.
Fig. 6 is a block diagram of PLL, Fig. 7 is an operation waveform diagram of the circuit in Fig. 6, Fig. 8 is a frame sync signal detection circuit diagram, Fig. 9 is a PLL 1ffi circuit diagram, and Fig. 10 is a block diagram of PLL. The diagrams are a diagram explaining the circuit operation of Figure 9, Figure 11, and Figure 1.
FIG. 2 is a flowchart showing the operation at the time of disk startup, and FIG. 13 is a diagram explaining an example of the operation at the time of search. Explanation of symbols of main parts 1...System controller 2...Pickup 4...Frame sync servo device 6...
Spindle driver 7...P L L 8...Demodulator 9...RAM 14...Phase comparator Applicant Pioneer Co., Ltd. Agent Patent attorney Fujimura Motohiko

Claims (2)

[Claims] (1) @Large interval inversion is n times (n is an integer greater than or equal to 1)
A rotation control method for a recording disk on which digital signals including continuous synchronization signals are recorded, in which the recording disk is once accelerated by supplying a predetermined constant voltage or current to a motor for a predetermined period of time in response to a rotation start command. The method is characterized in that a period of zero times the maximum inversion interval included in a reproduction signal subsequently reproduced by a pickup is detected, and the rotation of the recording disk is controlled using the detection signal. (2) Supplying a predetermined constant voltage or current smaller than the constant voltage or current during the acceleration operation to the motor in order to perform the operation of accelerating the recording disk and controlling the rotation of the disk using the detection signal. A patent characterized in that a control period (=1-) for maintaining disk rotation substantially constant is provided, and after the focus servo of the pickup is locked during the holding control period, a disk rotation control operation using the detection signal is performed. The method according to claim 1.