JPS5970314A - How to drive a switching circuit - Google Patents

Abstract

PURPOSE:To increase the number of switching circuits driven at the same time without requiring increase in package grounding pins by splitting the switching circuit into plural groups and adopting different switching timing to each group. CONSTITUTION:Data input signals A1-An are given respectively to the switching circuits 70-1-70-n of the 1st group, the circuits are on/off-controlled with the 1st switching control signal GA, and the 2nd and the 3rd groups are controlled similarly by signals GB and GC. Since a common impedance 40 is formed with bonding wires and package pins connected externally to the internal ground, a noise voltage is generated across the common impedance at on/off control, but the generation takes place spearately because the phase of the signals GA, GB, GC is different, and the number of switch circuits possible for simultaneous drive is increased in comparison with the case without grouping. Thus, the decrease in the common impedance due to increase in the grounding pins is avoided.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for driving a switching circuit in an integrated circuit, and in particular, a method for driving a switching circuit to which a low resistance load or a high capacity load is connected. Regarding.

[Prior art]

FIG. 1 shows a conventional switching circuit in an integrated circuit. In the figure, 10-1.10-2゜10-n is an AND gate, 20-1.20-2゜20-n is a switching transistor, and 30-1゜30-2.30-n is an external transistor of the integrated circuit. The connected resistive load 40 is a common impedance present between the integrated circuit's internal ground (1) and the integrated circuit's external ground (A). In this circuit, the data input signal I
When ++It and Ia are each at the 1" level, when a 1" level is applied to the switch control signal G, the switching transistors 20-1, 20-2, 20-0 are turned on, and the load resistor 30- is connected to the external power supply Va. 1.30-2.3
The load current flows through 0-n and further through the common impedance 40 toward the external ground point. Data input signal II + Ii! +1 is at the "0" level, the corresponding switching transistor is turned off, so no current flows through the load resistor.

The common impedance 40 consists of a series circuit of a ground line resistance and an inductance, and its equivalent circuit is as shown in FIG. 2(a). Neglecting the common impedance internal to the integrated circuit, the common impedance 40 is formed by the bond wire and package pins connecting the internal and external grounds.

Electricity Me flows through such a common impedance, and when it is turned on and off, a noise voltage is generated across the common impedance, which adversely affects the internal integrated circuit.

In FIG. 2(a), if the current flowing through the common impedance 40 is i, the resistance is r1, and the inductance is L, then
The shoe sound voltage ρ1 generated is as follows.

i ρ++=L−1ir・・・・・・・・・・・・
・・・・・・・・・・・・・・・(1)t Normal I) ■One example when using a P-type package: r=0.1(Ω), L=20×10−”( H).

Now, in the switching circuit shown in Figure 1, one transistor turns on and off the direct current of 50X10'' (A), and the switching time is 10XI O-@(S).
Then, when one transistor is turned on, the noise voltage ρ generated across the common impedance 40 is (
From equation 1), we get: It can be seen that the noise vehicle pressure due to inductance is dominant. Still, the noise withstand voltage ρ, hexagonal shape is shown in Fig. 2 (b).
It becomes like I7+. Therefore, if the allowable noise voltage is 4
00 mV, the number of loads that can be driven simultaneously in the conventional switching circuit shown in FIG. 1 is a little less than 4, and cannot satisfy the requirement of 8 to 32 loads being driven simultaneously. For this reason, the conventional method has been to provide a large number of "II2" pins connected to the package to reduce the common impedance under equal constraints.

However, this method inevitably requires a large package with a large number of pins, which has the disadvantage of increasing costs.

[Object of the present invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide a switching circuit driving method that can simultaneously drive a greater number of switches with a smaller number of grounding pins.

[Summary of the invention]

This study focused on the fact that the ringing voltage generated in the common impedance of the ground line is dominated by the back electromotive strength due to the inductance that occurs during the transition period between on and off of the current.
By dividing multiple switching circuits into multiple groups and making the switch timings of the multiple groups slightly different, the generation of noise voltage is dispersed. Significantly increases the number of drives that can be driven.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail according to the N-side.

In FIG. 3, 70-1.70-2.70-n.

80-1.80-2.80-n, 90-1.90=2.
90-n are switching circuits, and these switching circuits are divided into three groups in this embodiment.

That is, the first group and one switching circuit 70-
1.70-2.70-n each A+ * A2 +
A and ++ data inputs a are given, and the on and off states are controlled by the first switch control signal G. Similarly, the second group of switching circuits 80-1.80-
2.80-n are given data input signals Bl, B, , Ij, respectively, and the second switch control signal Ga
On and off are controlled by Furthermore, a third group of switching circuits 90-1.90-2.90-
Data input signals of C+, Ct, and C- are applied to n, respectively, and on and off are controlled by a third switch control signal GO.

A 60-piece switch system signal generation circuit uses the input control signal Gk as the source, and generates the switch control signals G A, GB+G
generate c. The switch control @41 signal generated by the switch control signal generating circuit 60 is as shown in FIG.

That is, the first switch control signal G is generated in the same phase as the input control signal G. Second switch control signal Q
The signal e is generated with a phase delayed by the time t1 from the first switch control signal GA. Just like that, the third switch control signal G
c is generated at a phase that is delayed by time t2 from the second switch control signal G8. Therefore, in the embodiment shown in FIG. 3, when the input divider j signal G is applied to the switch-based signal generation circuit 60, the noise voltage ρ generated across the common impedance 40. becomes as shown in Figure 4,
The generation timing of the sheath voltage is dispersed by time tI+'2. As a result, in the embodiment of the present invention in which a plurality of switching circuits are divided into three groups, three times as many switching circuits can be simultaneously driven as compared to the conventional method without increasing the noise voltage. In addition,
According to the present invention, if a plurality of switching circuits are divided into N groups, it is possible to drive them N times as many times as before, but the maximum number of groups to be divided depends on the allowable skew value between switching circuits. If the skew value is not limited, 114 additional ground pins will be required.

FIG. 5 1 shows the configuration of the switch control signal generation circuit 60. In the figure, 60-1 and 60-2 are delay elements, the switch control signal G is outputted after the input side (goods) signal G is switched, and GB delays the human control signal G by the delay element 60-1. will be output. It's a trench, Gl.
Qn is further delayed by the delay system 60-2 and outputted.

FIG. 6 shows one embodiment of a switching alpha signal generating circuit. In the figure, 60-3.60-4.60-
5.60-6 is an inverter circuit, inverter 60
-3 and 60-4 and 6o-5 and 60-6 each constitute one delay element.

Figure 7 shows another embodiment of the switching control signal generating circuit. In the figure, 60-7.60-8 is the resistance, 60-
9. 60-10 is a capacitor, resistor 60-7 and capacitor 60-9, resistor 60-8 and capacitor 60
-10 each constitute one delay element. These resistors and capacitors can be easily realized inside the integrated circuit using only a wiring material such as polysilicon. In this case, the anime game shown in Figure 1)10
-1.10-2.10-n should be composed of elements with sufficiently high input impedance, such as MO8I transistors.

〔Effect of the invention〕

According to the present invention, more switching circuits can be driven at the same station without increasing the number of grounding bins of the package. Therefore, it is possible to avoid increasing the size of the package due to the increase in the number of pins, and it becomes possible to manufacture an inexpensive integrated circuit.

[Brief explanation of drawings]

Fig. 1 is a conventional switching circuit diagram, Fig. 2 is an equivalent circuit of common impedance and a waveform diagram of noise voltage, No. 31￥1
is a switching circuit diagram of the present invention, FIG. 4 is a time chart of switch control signals and noise voltage, FIG. 5 is a configuration diagram of a switch control signal generation circuit of the present invention, and FIG. 6 is a switch control signal generation circuit of the present invention. FIG. 7 is a diagram showing another embodiment of the switch control signal generating circuit of the present invention. 60...Switch control signal generation circuit, 70-1 to 70
-1...Switching circuit, 80-1 to 80-n...
・Switching circuit, 90-1 to 90-n...Switching circuit, 60-1.60-2...Delay (9) Hair bundle, 60-3 to 60-6...Inverter, 60-7
, 60-8...Resistor, 60-9.60-10...Capacitor. (10) V 3 Figure 60 Figure 4・-4"1→--w "Calculation 50 1st 1f)

Claims (1)

[Claims] 1. A plurality of switching circuits that turn on and off in synchronization with a switching system signal according to a data input signal are divided into a plurality of groups, and a plurality of switch control No. 11 corresponding to each of the plurality of groups is provided. A switch control signal generation circuit is provided to generate a switch control signal, and the switch control signal generation circuit generates a plurality of switch control signals whose rising and falling timings are equal and is divided into the plurality of groups. A method for driving a switching circuit, comprising independently driving each of the switching circuit groups.