JPS5968789A - Automatic rhythm performance unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION 1/IJ This invention relates to an automatic rhythm performance device.

In conventional electronic musical instruments, pattern data for multiple types of rhythms is stored in a ROM (l+-do only memory) in units of two measures, for example, and then the performer specifies the type of rhythm using a button in advance and stores the data in the RAM ( There is a system in which when IIJ rhythms of a specified type are input into a random access memory (random access memory), they are read out from the RAM in the specified order, allowing automatic rhythm performance.

However, in the case of conventional electronic musical instruments that allow this type of rhythm progression to be programmed, if you want to repeat a certain rhythm multiple times, it is necessary to operate the rhythm designation button multiple times.
The input operation becomes complicated, and the RAM usage area also decreases.
It has the disadvantage that it requires as many repetitions as it needs to be repeated, which increases the capacity.

Furthermore, each rhythm read from the ROM as the rhythm progresses has a constituent unit of, for example, two measures as described above, and as a result, each rhythm is the same measure unit, so there is little musical variation. Sometimes it got monotonous. Therefore, it is conceivable to set a rhythm progression by combining rhythms with different lengths of measures that make up a 1.1-2- pattern, but in that case, when automatically playing, Because each rhythm is read out in the same measure unit, the second half of a certain rhythm may not be played, or conversely, if the rhythm has a short number of measures, there may be no accompaniment between the rhythm and the next rhythm. It could happen. Therefore, in order to prevent such inconveniences, a separate processing circuit is required, which has the drawback of complicating the configuration.

This invention was made against the background of the above-mentioned circumstances.
The object thereof is to provide an automatic rhythm performance device that allows continuous performance designation that can be repeated an arbitrary number of times for each of a plurality of rhythms, and allows the rhythm progression to be programmed.

Hereinafter, the present invention will be described in detail with reference to the drawings. 1st
The figure is a block circuit diagram of an electronic musical instrument equipped with an automatic rhythm playing device. In the figure, a keyboard 1 is provided with a plurality of keys, and the output signals from each key are input to a CPU (central processing unit) 2 and processed. This CPU 2 is a circuit that processes all operations of this electronic musical instrument, and is composed of a processor. The switch input section 3 includes a rhythm designation switch 3A for designating a 10i rhythm such as Rock L Rock 11, Rock III, Rumba, etc., and a rhythm designation switch 3A that manually controls the number of times the rhythm designated by this rhythm designation switch 3A is repeatedly played. numeric keypad 3B for inputting end chords (described later), end key 3C1 for inputting end chords (described later), mode changeover switch 3D for specifying each mode of rhythm set mode (S) and play mode (P), and several other keys for executing automatic chord performance. Various switches and keys are provided, such as a switch and a tone designation switch.

When the output of the operation keys manually played on the keyboard 1 is input to the CPU 2, the CPU 2 sends musical tone generation information to the musical tone generating section 4 to generate a musical tone signal. This musical tone signal is emitted as a musical tone from the speaker 5 via an amplifier (not shown) or the like.

The ROM (read only memory) 6 has one of the locks, etc.
Zero types of rhythm pattern data are stored. FIG. 4 shows the rhythm pattern of rock ■. This rock ■ has a pattern for two measures, and one measure consists of eight beats. And in the figure, HH, SD', BD,
HC and LC represent percussion instruments such as bibat, snare drum, bass drum, /\Ikonka, and low-contact power, respectively;
The marks indicate that each instrument sound is produced on the indicated beat.

151DLt Lock I rhythm pattern data RO
The memory state in M6 is conceptually shown. In the ROM 6, each beat is composed of 8-bit data as well as pattern data of nine other rhythms. and the lowest bin) (LSB
) corresponds to the Haihara) (HH) instrument, and 2, 3.
4.5.6.7 bits are cymbal (SY), low contrast power (LC), hyunga (H (1), claves (C), respectively.
L), snare drum (SD), bass drum (HD) and G. Then, in the data of the 1st to 7th bits, “l
The data II means that the corresponding rhythm tone circuit in the rhythm sound generation section 7 (Fig. 1) is driven to generate the rhythm sound, and the data "'0" is not driven and the sound is generated. It means not to let it happen.

Also, the 8-bit HCMSR) is provided to indicate the end of the rhythm pattern with data "1'."0 Figure 6 shows the rhythm pattern of rock ■, and as shown, it is only for one measure. Fig. 7 shows the rhythm pattern data in ROM 6.Furthermore, Fig. 8 shows the rhythm pattern of rock ■, which is only for one measure as shown in the figure.And Fig. 9 shows the rhythm pattern in ROM 6. The same applies to the other seven rhythms such as Rumba, and their illustration is omitted.

A programmable RAM (random access memory) 8 is a memory for rhythm progression storage in which data such as the type of rhythm and the number of repeats inputted by operating the rhythm designation switch 3A and the numeric keypad 3B are written as pair data. Data reading and writing operations are controlled by a read/write control signal R/W output from the CPU 2.

Also, S register 9, A register 10, C register 11,
The repeat register 12 and the work register 13 are registers used when writing and reading data into the programmable RAM 8. Among these, the data of the number of repeats is inputted to the repeat register 12 and given to the comparator 14. Each time one rhythm performance is completed, the data is decremented by 1, and the comparison unit 14 determines whether the data has become "0" or not, that is,
A comparison result signal for determining whether or not the rhythm performance has been performed the specified number of times is output to the CPU 2. Further, the work register 13 also receives rhythm pattern data read out from the ROM 6, and the input data is provided to the rhythm sound creation section 7 and the detection section 15. The detection unit 15 determines whether the MSB of the rhythm pattern data is -1, 5 or not, that is, whether or not the MSB of the rhythm pattern data is -1, 5, and sends the determination result signal to the CPU.
Give to 2.

The oscillator wML16 outputs a reference signal and supplies it to the CPU 2 to control the entire circuit. Also, timer 17
It is reset by the reset signal R from P U 2, then inputs the clock CLK from the CPU 2 to perform a timekeeping operation, and when the carry signal C is output, it is given to the CPU 2. Thus, one timing operation of the timer 17 corresponds to the duration of one beat.

Next, the operation of the above embodiment will be explained. As shown in Figure 10, ROM6 is currently locked from address X to a specified location.
It is assumed that pattern data for the rhythms of ``Rock II'' and ``Rock I'' are stored from the Y@ address to the predetermined address, and further from the 2nd address to the 191 address, respectively. Note that illustration of other rhythms is omitted.

First, the operation when setting the rhythm progression in the programmable RAM 8 will be explained. Mode changeover switch 3D
to rSJ and set the rhythm set mode. As a result, execution of the flowchart shown in FIG. 2 is started. Immediately, in the process of step S, the start address L of the area where the rhythm progression of the programmable RAM 8 will be stored from now on is determined.
(11th [ ] REFERENCE! ) is set in the S register 9. Next, this start address L is transferred to the A register 10 (step S2). Next, the CPU 2 outputs a key common signal for key sampling processing to be executed periodically to the keyboard 1 and the switch manual section 3, and determines whether or not there is a key-in signal (steps S3 and S4). First, when the rhythm designation switch 3B is operated to designate the lock I, that signal is input to the CPU 2 and processed, and the CPU 2 determines in step S6 that it is the end gear 3.
It is determined whether or not the end code is input by C. Since the answer is currently no (N), the process proceeds to step ScI, and it is determined whether or not it is the input of lock (2). Since the answer is yes (Y), the process proceeds to step 812 and the programmable RAM
Write the start address X of lock I to address L of 8 (first
(See Figure 1). Then, the process proceeds to step 816, where the value of the A register 10 is increased by 1 to L+1, and step 81? Proceed to. Then, when you operate the numeric keypad 3B and input the number of repeats for lock ■, for example 4, the key force is detected in step S1□, and the L+ of the programmable RAM 8 is detected.
The number of repeats, 4, is written to address 1. (Step 81
8). Next, in step SI9, the A register 10 is incremented by 1, and its value becomes L+2. Then step S,
to return to.

Next, when lock ■1 is specified, after steps 83 to S7 are processed, it is determined in step S8 21, the process proceeds to step S14, and lock ■ is specified at address L+2 of RAM8.
The starting address Z of is written (FIG. 11). Next, in step 816, the value of A register 10 changes to L+3,
Further, when the number of repeats 3 is inputted using the numeric keypad 3B, the number of repeats 3 is written to the address L+3 of the RAM 8 through each process of step SIT 818. and A register l
After the value of O is increased by +1 to become L+4, the process returns to step S3.

Next, when lock ■ is specified, after the processing of steps 83 to S6, this is determined in step S7, and step S'
The process advances to step s, and the start address y of lock (2) is written to address L+4 of the programmable RAM 8. The process then proceeds to step SI6, where the value of the A register 10 becomes L+5.

Next, input the number of repeats 1】- and step SIT,
At S+6, the number of repeats 1 is stored in the address L+5 of the RAM 8 (7-1), and then the A register 10 is incremented by 1 to become L+6, after which the process proceeds to step S3.

Next, when the end key 3C is turned on to finish inputting the rhythm progression, this is determined in step S, and an end code END is written to address L 106 of the programmable RAM 8, and the rhythm progression input operation is performed. or end.

FIG. 11 shows the final state of RAM8.

The same applies to the input of other rhythms; for example, step Sil and SIO are for rumba and bossa nova.

Next, an explanation will be given of the operation when performing automatic accompaniment as described above (according to the inputted rhythm progression - desired rhythm σ).

First, the mode selector switch 3D is set to rPJ, and the play mode is set to 1. As a result, the flowchart shown in FIG. 3 starts to be executed. That is, the first address in the S register 9 is transferred to the A register 10 (step M1),
Next, data X at address L of the programmable RAM 8 is set in the C register 1 (step M2). Next A
Register 10 is incremented by 1 and becomes L+1 (step Ms
).

Next, the repeat count 4 at address L+1 of RAM 8 is set in the repeat register 12 (step M4).

Next, the CPU 2 outputs the reset signal R to the timer 17, and then applies the clock CLK to start the timekeeping operation (
Step M,). Further, 8-bit data "01000001" of the first beat of lock (2) is read out from address X of the ROM 6 in accordance with data X in C register 11 (see FIG. 5) and transferred to work register 13. And this 8
The bit data +t, 'J is given to the rhythm sound creation unit 7 and the detection unit 15, and as a result, the rhythm sound generation unit 7 drives the bass drum and heihet rhythm sound sources, and the rhythm sound of the first beat is Sound is emitted from the speaker (steps M6, M
7). Next, whether or not the carry signal C is output from the timer 17 in step M8 is f! II. It is determined whether one beat's worth of time has elapsed or not, and when the carry signal C is output and applied to the CPU 8, the process proceeds to step M, where the 8 in the work register 1:3 is It is determined whether the MSB of the bit data is "111", that is, whether it is the end of the lock pattern (2), and since it is rNJ, the process proceeds to steps M and o, and the C register]1 is incremented by +1, resulting in X+1, and step M
Proceed to 6. Then, the timer 17 is reset and the timing operation starts again, and the 8-bit data [000
00001J is read from the ROM 6 and transferred to the work register 13 (step M6).

Therefore, the second beat σ) rhythm sound is emitted, and when the timer 17 outputs the carry signal C, it is determined whether the MSB of the 8-bit data is "1" or not, and then the C register 11 is incremented by 1. becomes X+2, which is also taken at step M (
each process of steps M, ~M, 0).

The same is true for beats 3 to 15, and step M5
~MH6 is repeated. When the 166th beat 8-bit data r], ]00000]J is read out, it is determined in step S that the MSH is "]゛°, and the result is "Y", and the process proceeds to step Sll.

As a result, the A register decreases by -1 and becomes L. Then R
The data X at the L address of AM8 is transferred to the C register 11 (step M+2), and the A register 10 is further increased by +l and becomes L+1 (step M13), and the repeat register 12 is locked by -1 (4 times). It is determined whether or not the rhythm performance has ended (7)) (note that the CPU 2 makes this determination based on the comparison result signal from the comparison section]4).

1N", the process returns to step M5 (step M1
．． ). Then, the second performance of Rock ■ begins.

The second, third, and fourth performances are performed using the same processing steps as the first performance. Each time the performance ends, the repeat register 12 is incremented by -1, and at the end of the fourth performance, the data becomes "0". Therefore, that is step M8. If it is determined by the processing of , it becomes rYJ and the process proceeds to step M, 6, where the A register 10 is incremented by +1 and becomes L+2. Then, data Z at address L+2 of RAM 8 is transferred to work register 13 (step M, 7
).

Then, the detection unit 15 determines whether the data is the end code END, and since it is "N", the process returns to step M2.
The rhythm performance of Rock 1■ begins (step M1).
8).

The automatic performance operation according to the rhythm progression in RAM 8 for Rock ■■ and Rock ■ is the same as that for Rock I, and is played three times and once, respectively. Then, when the performance of rock ■ is finished, the data in the A register 10 becomes L+6 due to the processing in step M16, and the data in the work register 1 becomes L+6.
3 to RAM 8 L + 6 address to end code EN
D is read. Therefore, the code is determined by the determination processing in steps M and 8, and the result is "Y", and step M
Return to step 1 and repeat the set rhythm progression. In addition, when the keys of the keyboard 1 are not operated in accordance with the above-mentioned rhythm performance, the CPU 2 sends a musical tone generation image signal to the musical tone generating section 4 to generate the musical tone signal, and then outputs the musical tone signal to the speaker 5.
The music murmurs along with the rhythmic sound.

Incidentally, in the above embodiment, the type of rhythm is set to 0, but this number can be changed if there is a plurality of rhythm types. Also, one constituent unit of the rhythm l\ is two measures and one measure negative j, but the length is also arbitrary. Further, the electronic musical instrument may not have an automatic performance device built-in, but may be a standalone device.

As explained above, the present invention provides an automatic rhythm playing device that allows each of a plurality of rhythms to be played by specifying an arbitrary number of repetitions and allows the rhythm progression to be freely programmed. It is advantageous because it is less monotonous and requires less memory capacity to set the rhythm progression. Furthermore, by setting an end mark at the end of the rhythm pattern data, if the pattern contains rhythms with different lengths of measures, the original rhythm will be played for the specified number of times for all measures. It also has the advantage of not causing inconveniences such as repeated rhythm performances and interruptions in the middle.

[Brief explanation of the drawing]

Fig. 1 is a block circuit diagram of an electronic musical instrument according to one embodiment of the present invention, Fig. 2 is a flowchart explaining the operation when presetting the rhythm progression, and Fig. 3 is the operation of rhythm performance using the preset rhythm progression. The flowcharts to be explained, FIG. 4, FIG. 6 to FIG.
7 and 9 respectively show the locks 11,
FIG. 10 is a diagram conceptually showing the storage state of each rhythm pattern data in the ROM 6 of the lock ITI.
FIG. 11 is a diagram conceptually showing the storage state of the lock (2), etc. in No. 6, and FIG. 11 is a diagram showing the storage state of the programmable RAM 8. 2...CPU, 3A...Rhythm specification switch, 3B numeric keypad, 3C...End key,
3D...Mode changeover switch, 6...
・ROM, 7... Rhythm sound creation section, 8...
...Programmable RAM, 9-13...Register, 14...Comparison unit, 15...Detection 1
7- Output MI, l 7...Timer. Patent applicant: Casio Computer Co., Ltd. JP 59-68789 (7) Figure 2 Figure 4 Figure 8 Figure 6

Claims (2)

[Claims] (1) A first memory means for storing a plurality of types of rhythm pattern data, a means for specifying the type of rhythm, and a repeat count for repeating the rhythm pattern data specified by the specifying means. means and
a second memory means for storing each data of the rhythm designated by the said designation means and the number of repeats inputted by the said input means; and this second memory means generates a rhythm sound based on each of the stored data. 1. An automatic rhythm performance device comprising means for performing automatic rhythm performance. (2) The automatic rhythm performance device according to claim 1, wherein the rhythm pattern data includes an end mark indicating the end of one turn.