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JPS5967629A - Electrostatic attracter - Google Patents

Electrostatic attracter

Info

Publication number
JPS5967629A
JPS5967629A JP57177518A JP17751882A JPS5967629A JP S5967629 A JPS5967629 A JP S5967629A JP 57177518 A JP57177518 A JP 57177518A JP 17751882 A JP17751882 A JP 17751882A JP S5967629 A JPS5967629 A JP S5967629A
Authority
JP
Japan
Prior art keywords
wafer
force
voltage
peeling force
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57177518A
Other languages
Japanese (ja)
Other versions
JPH0263304B2 (en
Inventor
Shoichi Tanimoto
昭一 谷元
Yukio Kakizaki
幸雄 柿崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nikon Corp
Original Assignee
Nikon Corp
Nippon Kogaku KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nikon Corp, Nippon Kogaku KK filed Critical Nikon Corp
Priority to JP57177518A priority Critical patent/JPS5967629A/en
Publication of JPS5967629A publication Critical patent/JPS5967629A/en
Publication of JPH0263304B2 publication Critical patent/JPH0263304B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Jigs For Machine Tools (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To bring attracting force in the case when an object to be attracted is taken away of an attracting base to approximately zero by measuring the attracting force of the object and generating erased charges corresponding to the measuring value in the attracting base. CONSTITUTION:A wafer 1 is placed on electrodes 4, 5, the surfaces thereof are coated with insulating layers 4a, 5a, and voltage is applied to the electrodes 4, 5 from a voltage generating section 10, thus attracting and fixing the wafer 1 to the electrodes 4, 5. Voltage applied to the electrodes 4, 5 is brought to zero when removing the wafer 1, and the attracting force of the wafer 1 is measured by an exfoliating-force generating section 13, a displacement member 12, a positional detector 14 and a chucking control section 15. Voltage of polarity reverse to one in case of attraction is applied to the electrodes 4, 5 so that attracting force is minimized in response to the measuring value. Accordingly, charges charged to an insulating layer 3 such as silicon oxide coating the surface of the wafer 1 are removed, and the wafer 1 is not subject to stress and can be removed. The wafer 1 is not attracted to an arm for carrying, etc. by residual charges.

Description

【発明の詳細な説明】 本発明は対象物を静電吸着する装置に関し、特に半導体
ウェハを平面状に強制し、吸着固定するための静電吸着
装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for electrostatically adhering an object, and more particularly to an electrostatic adsorbing apparatus for forcing a semiconductor wafer into a flat shape and adsorbing and fixing the object.

サブミクロンの大きさのパターンを効率よく加工できる
リソグリフイー装置として真空中にマスクとウェハな置
きX線源から有限の距離だけ離れた位置で露光を行なう
X線露光装置が考えられてきた。この種の装置において
は真空中でウェハの面を平面状に固定保持する必要があ
り、この必要を満たすものとして静電気力を利用したチ
ャッキング装置が提案されてきた。しかしながら、静電
気力を利用したチャック(吸着台)によってシリコンウ
ェハ(以下ウェハと称する)等を吸着する場合、表面に
シリコンの酸化膜や窒化膜等の絶縁層が形成されている
ことが多く、吸着後に吸着台の印加電圧をO■にしても
ウェハと吸着台との間に吸着力が働き続けることがある
、っこのため固定された状態からウェハをはずせながっ
たり、例え外力を加えてはずしたとしても吸着台以外の
導電体の板にウェハ裏面を接触させるとそこにウェハが
吸着されてしまうという欠点があって実用化には至らな
かった。 この現象の生ずる理由はウニへのチャック時
に、吸着台の電極から加えられる電場によってウェハ内
に誘起された電荷が酸化シリコン層等の絶縁層に入り、
吸着台の電極の印加電圧なO■としても電荷が絶縁層に
捕えられたまま移動できずこの電荷により吸着台以外の
他の金属板内に電荷が誘起されるからである。
As a lithography system that can efficiently process submicron-sized patterns, an X-ray exposure system has been considered that places a mask and wafer in a vacuum and performs exposure at a position a finite distance away from an X-ray source. In this type of apparatus, it is necessary to fix and hold the surface of the wafer in a flat state in a vacuum, and chucking apparatuses that utilize electrostatic force have been proposed to meet this need. However, when a silicon wafer (hereinafter referred to as a wafer) is adsorbed using a chuck (adsorption stand) that uses electrostatic force, an insulating layer such as a silicon oxide film or nitride film is often formed on the surface, Even if the voltage applied to the suction table is later changed to O■, the suction force may continue to act between the wafer and the suction table.This may make it impossible to remove the wafer from the fixed state, or even if external force is applied. Even if it were removed, if the back side of the wafer was brought into contact with a conductive plate other than the suction table, the wafer would be attracted there, which prevented it from being put to practical use. The reason why this phenomenon occurs is that when the sea urchin is chucked, the electric charge induced in the wafer by the electric field applied from the electrode of the suction table enters the insulating layer such as the silicon oxide layer.
This is because even if the voltage applied to the electrode of the suction table is O2, the charge remains trapped in the insulating layer and cannot be moved, and this charge induces charges in other metal plates other than the suction table.

本発明はこれらの欠点を解決し、吸着時の印加電圧をO
■とした後、対象物と吸着台、あるいは他の導体との間
に働く吸引力を実用上問題のない程度に減少できるよう
にした静電吸着装置を提供することを目的としている。
The present invention solves these drawbacks and reduces the applied voltage during adsorption to O
(2) The object of the present invention is to provide an electrostatic adsorption device that can reduce the attraction force acting between the object and the adsorption table or other conductor to a level that poses no problem in practice.

すなわちこの目的を達成するだめの本発明の静電吸着装
置は、導電体又は半導体等の対象物を載置して静電吸着
する吸着台と、吸着された対象物の吸着力を計測する測
定手段と、対象物の?1/電荷を消去するように前記測
定手段の計測値に応じた電荷量の電荷を前記吸着台に発
生させる消去電荷発生手段とを備え、対象物を前記吸着
台から取りはずす際に吸着力を略零にするようにしたこ
とを特徴とするものである。
In other words, the electrostatic adsorption device of the present invention to achieve this purpose includes a suction table on which an object such as a conductor or semiconductor is placed and electrostatically adsorbed, and a measurement device that measures the adsorption force of the adsorbed object. Means and object? 1/ Erasing charge generating means for generating an electric charge on the suction table in an amount corresponding to the measured value of the measuring means so as to erase the electric charge, and the suction force is reduced when the object is removed from the suction table. It is characterized by being set to zero.

ひとつの態様において、前記測定手段は、対象物に当接
して該対象物に前記吸着台からの剥離力を発生させると
共にその剥離力を吸着力として検知する剥離力発生手段
をJL Gu シ、この場合、該剥離力発生手段の剥離
力は対象物を破損しない大きさに制限されている。
In one embodiment, the measuring means includes a peeling force generating means that comes into contact with an object to generate a peeling force from the adsorption table on the object and detects the peeling force as an adsorption force. In this case, the peeling force of the peeling force generating means is limited to a magnitude that does not damage the object.

また前記消去電荷発生手段は、吸着時とは逆極性でかつ
絶対値が順次大ぎくなる逆電圧を断続的に前記吸着台に
印加すると共に、該逆電圧の印加後、前記剥離力発生手
段によって剥離力を検知することを順次繰返し、検知さ
れた剥離力が最小となったときの逆電圧値を、吸着力を
略零にするための電圧とするようになされている。
Further, the erasing charge generating means intermittently applies a reverse voltage having a polarity opposite to that at the time of attraction and whose absolute value increases sequentially to the suction table, and after applying the reverse voltage, the peeling force generating means Detection of the peeling force is sequentially repeated, and the reverse voltage value when the detected peeling force becomes the minimum is set as the voltage for reducing the adsorption force to approximately zero.

本発明を図示の実施例と共に説明すれば以下の通りであ
る。
The present invention will be described below with reference to the illustrated embodiments.

第1図は本発明の実施例を示才ね能ブロックを添置した
断面図である。半導体ウェハ1の上面にはパターン2が
形成され、裏面は酸化シリコン等の絶縁層6によって覆
われているものとする。4と5はウェハ1を吸着する吸
着台(固定基台)を構成する平担な一対のta極であっ
て、電極4,50表面は絶縁層4a及び53によって覆
われている。さらに電極4と5には導線8と9によって
電圧発生部10からの電圧が直列接続された抵抗11を
介して印加される。剥離力発生部13は、偏位部材12
を偏位させて矢印Zの向きの任意の大きさの力を発生さ
せ、ウェハ1に直接この力を加えてウェハ1を電極4,
5から遠ざけようとする力、すなわち剥離力を発生する
FIG. 1 is a sectional view showing an embodiment of the present invention with a functional block attached thereto. It is assumed that a pattern 2 is formed on the top surface of the semiconductor wafer 1, and the back surface is covered with an insulating layer 6 such as silicon oxide. Reference numerals 4 and 5 are a pair of flat TA electrodes constituting a suction table (fixed base) for suctioning the wafer 1, and the surfaces of the electrodes 4 and 50 are covered with insulating layers 4a and 53. Furthermore, a voltage from a voltage generating section 10 is applied to the electrodes 4 and 5 through conductive wires 8 and 9 via a resistor 11 connected in series. The peeling force generating section 13 is connected to the deflection member 12
is deflected to generate a force of arbitrary magnitude in the direction of arrow Z, and this force is applied directly to the wafer 1 to move the wafer 1 to the electrodes 4,
A force that tries to move away from 5, that is, a peeling force is generated.

また、剥離力発生部13には偏位部材12のZ方向の応
力すなわちウェハ1の吸着力を測定するストレンゲージ
粉・の吸着力測定手段か組込まれている。
Further, the peeling force generating section 13 incorporates a strain gauge powder adsorption force measuring means for measuring the Z-direction stress of the deflection member 12, that is, the adsorption force of the wafer 1.

前記剥ll;i#力の大きさは外部より制御し得るもの
であるのは述べるまでもない。
Needless to say, the magnitude of the peeling force can be controlled from the outside.

例えば剥離力発生部16にLモータや電磁ソレノイド等
をA(動源として含み、その駆動力をカムやリンク七1
1構等を用いて偏位部材12に伝えるようになっている
。また駆動力をバネ材を介して(i41位部相12に伝
え、そのバネ材のたわみ五1からウェハ1の吸着力を測
定するようにしてもよい。
For example, the peeling force generating section 16 includes an L motor, an electromagnetic solenoid, etc.
The information is transmitted to the deflection member 12 using one structure or the like. Alternatively, the driving force may be transmitted to the phase 12 via a spring material (i41), and the adsorption force of the wafer 1 may be measured from the deflection 51 of the spring material.

位置検出器14は、具体的にけ光電的な非接触のリミッ
トスイッチ等であり、偏位部材12の偏位を検出するも
のである。
The position detector 14 is specifically a photoelectric non-contact limit switch or the like, and detects the deflection of the deflection member 12.

チャッキング制御部15は消去電荷発生手段としても働
く前記電圧発生部10の出力電圧の制御、剥離力発生部
13で発生するq1jlJj力の制御を行なうと共に、
位置検出器14の位置検出信号を入力として装置全体を
統括制御するものである。
The chucking control section 15 controls the output voltage of the voltage generation section 10, which also functions as an erase charge generation means, and controls the q1jlJj force generated by the peeling force generation section 13.
The position detection signal from the position detector 14 is input to centrally control the entire device.

ここで、吸着力測定手段を含む剥離力発生部16と位置
検出器140作用について、第2図(a入(b)を用い
て詳述する。第2図(a)は、剥離力発生部13の剥離
力Fを縦軸に定め、時間tを横軸に定めた特性図であり
、第2図(b)は、縦軸に偏位量Zを定め、横軸に時間
tを定めた位置検出器14の特性図である。この剥離力
は、例えば前述のように偏位部材12の応力を測定する
ストレンゲージ等の応力センサによってel“測される
。今、詩n■0で、偏位部材12がウェハ1に当りでし
たものとする。剥離力発生部13は、時間0がらtsま
で偏位部材12をウェハ1がtl[4,5からもち上が
る方向に単調に偏位させるカを発イ1′する。
Here, the operation of the peeling force generating section 16 including the adsorption force measuring means and the position detector 140 will be explained in detail using FIG. 2 (a and (b)). Fig. 2 (b) is a characteristic diagram in which the peeling force F of No. 13 is set on the vertical axis and the time t is set on the horizontal axis. It is a characteristic diagram of the position detector 14. This peeling force is measured by a stress sensor such as a strain gauge that measures the stress of the deflection member 12 as described above. It is assumed that the deflecting member 12 hits the wafer 1.The peeling force generating unit 13 monotonically deflects the deflecting member 12 in the direction in which the wafer 1 is lifted from tl[4,5] from time 0 to ts. The power is emitted 1'.

そして時間t8で、剥離力はウェハ1と電極4,5との
吸着力よりも大きい値F■となり、ウェハ1は電極4,
5から離れる。一方、位置検出器14で検出される偏位
長は、時間0がらtsまでの吸着中は位IZ、であり、
時間ts  でウェハ1がN極4゜5から離れると、位
置Z2になる。そこでチャッキング制御部15は時間t
Sで位置検出器14が出力する位置Z1から位置Z2ま
での検出信号に応答して、剥離力発生部13の剥離力発
生を中止する。これによって剥離力は急峻に零となり、
偏位部材12が元に戻ってウェハ1は第2図(b)のよ
うに再び電極4,5に吸着される。また剥離力発生部1
3は剥離力がウェハ1の破損を招く最大値Frn a 
x を越えないように、すなわちFv<Fmaxに制限
されている。これは応力センサで容易に検出制御できる
。このように、剥離力pv を測定することによってウ
ェハ1の吸着力が求められる。
Then, at time t8, the peeling force reaches a value F■ larger than the adhesion force between the wafer 1 and the electrodes 4 and 5, and the wafer 1 is removed from the electrodes 4 and 5.
Stay away from 5. On the other hand, the deviation length detected by the position detector 14 is the position IZ during adsorption from time 0 to ts,
When wafer 1 leaves N-pole 4°5 at time ts, it is at position Z2. Therefore, the chucking control section 15 controls the time t.
In response to the detection signal from the position Z1 to the position Z2 output by the position detector 14 at S, the peeling force generating section 13 stops generating the peeling force. As a result, the peeling force sharply drops to zero,
The deflecting member 12 returns to its original position and the wafer 1 is again attracted to the electrodes 4 and 5 as shown in FIG. 2(b). Also, the peeling force generating part 1
3 is the maximum value Frn a of peeling force that causes damage to wafer 1
x, that is, Fv<Fmax. This can be easily detected and controlled using a stress sensor. In this way, the adsorption force of the wafer 1 can be determined by measuring the peeling force pv.

次に、ウェハ1を吸着し、さらに取りはずす動作につい
て説明する。吸着の際、チャッキング制御部15は電圧
発生部10が例えば電極4を正、電極5を負とするよう
な直流電圧を出力するように制御する。この電圧は数百
ポルト程度である。
Next, the operation of sucking the wafer 1 and then removing it will be explained. During adsorption, the chucking control unit 15 controls the voltage generation unit 10 to output a DC voltage that makes the electrode 4 positive and the electrode 5 negative, for example. This voltage is on the order of several hundred ports.

これにより、ウェハ1の電極4との接触面側には負電荷
が誘起され、ウェハ1の電極5との接触面側には正電荷
が誘起され、ウェハ1は電極4,5に静電気力により吸
着される。
As a result, a negative charge is induced on the side of the wafer 1 that is in contact with the electrode 4, and a positive charge is induced on the side of the wafer 1 that is in contact with the electrode 5, and the wafer 1 is caused by the electrostatic force on the electrodes 4 and 5. It is adsorbed.

このウェハ1を取りはずすには、まず電極4゜5に印加
する電圧を零とする。その後、チャッキング制御部15
は前述のように剥離力発生部16と位置検出器14を用
いて、ウェハ1の吸着力を計測する。尚、剥離力発生部
13と偏位部材12によって、ウェハ1 ’k 電極4
 、5からはがしても、ウェハ1には依然として電荷が
保存されている。
In order to remove the wafer 1, first the voltage applied to the electrode 4.degree. 5 is made zero. After that, the chucking control section 15
As described above, the adsorption force of the wafer 1 is measured using the peel force generator 16 and the position detector 14. In addition, by the peeling force generating part 13 and the deflection member 12, the wafer 1 'k electrode 4
, 5, the charge is still stored in the wafer 1.

したがって偏位部材12を元に戻しても、ウェハ1の残
留電荷のために、ウェハ1は電極4,5に吸着される。
Therefore, even if the deflecting member 12 is returned to its original position, the wafer 1 is attracted to the electrodes 4 and 5 due to the residual charge on the wafer 1.

さて、吸着力が計測されると、?iL圧発圧部生部10
の吸着力が最小又は琴となるように、吸着時とは逆極性
の′Tri円を所定時間、電極4,5間に印加する。こ
の逆極性電圧の大きさや印加時間は、ウェハ1の吸着時
の帯電荷量によって決まる。その帯電荷量はもちろん吸
着力に応じたものてあイ)。
Now, what happens when the adsorption force is measured? iL pressure generating part 10
A 'Tri circle with a polarity opposite to that at the time of attraction is applied between the electrodes 4 and 5 for a predetermined time so that the attraction force becomes minimum or koto. The magnitude and application time of this reverse polarity voltage are determined by the amount of charge when the wafer 1 is attracted. Of course, the amount of charge depends on the adsorption force).

このように本実施例によれは、ウェハ1を1は極4゜5
から取りはずす際為ウェハ1の帯11L荷は除去されて
いるので、ウェハ1は何ら応力を受け1”に取りはずせ
る。また、ウェハが搬送用のアーム等にウェハ残留電荷
によって吸着することがな℃・ので、ウェハ1をただち
に次の処理工程に進めることができ、半導体装置の製造
工程の自動化に極めて有益である。
In this way, according to this embodiment, the wafer 1 is placed at a pole of 4°5.
Since the band 11L load of the wafer 1 has been removed, the wafer 1 can be removed at 1" without any stress. Also, the wafer will not be attracted to the transfer arm or the like due to the wafer's residual charge. - Therefore, the wafer 1 can be immediately proceeded to the next processing step, which is extremely useful for automating the manufacturing process of semiconductor devices.

ところで、」二記実施例ではウエノ1を取りはずすたび
に剥離力発生部13をかならず動作させなければならず
、また逆極性の電圧を大きさ又(]、時間に関して印加
し過ぎると、ウェハ1は再び帯電して吸着力が残留して
しまうことにブよる。
By the way, in the second embodiment, it is necessary to operate the peeling force generating section 13 every time the wafer 1 is removed, and if a voltage of opposite polarity is applied too much in terms of magnitude or time, the wafer 1 This is due to the fact that it becomes charged again and the adsorption force remains.

一般に、集積回路の製造時の工程には多様性があり、ウ
ェハ表面の酸化シリコンの層にしてもその厚さや組織構
造が様々である。しかし−1種類の集積回路を製造する
工程におけるウェハ同志、いわゆる同一ロット内では、
ウェハ間の酸化シリコンの厚さや物性はばらつきが小さ
く抑えられている。そこひ、1つのロフト内におけるウ
ェハについて静N1吸着後の帯電解除の方法を本発明の
他の実施例として述べる。
Generally, there are variations in the manufacturing process of integrated circuits, and the thickness and structure of the silicon oxide layer on the wafer surface also vary. However, in the process of manufacturing one type of integrated circuit, wafers within the same lot,
Variations in the thickness and physical properties of silicon oxide between wafers are kept small. As another embodiment of the present invention, a method of destaticizing a wafer in one loft after static N1 adsorption will be described.

第31M(a)は電圧発生部10の動作を説明するグラ
フで、t+Q軸に時間、縦軸に発生電圧をとって示した
特性図である。
31M(a) is a graph explaining the operation of the voltage generating section 10, and is a characteristic diagram in which time is plotted on the t+Q axis and generated voltage is plotted on the vertical axis.

ウェハ1を吸着している時は電圧発生部10からは電圧
■0が出力されているが、吸着を終了させる時には電圧
O■になり、時間to  において、上記で説明した剥
離力F(V)の測定が行なわれる。
When the wafer 1 is being attracted, the voltage generator 10 outputs a voltage of 0, but when the wafer 1 is being attracted, the voltage becomes O, and at time to, the above-described peeling force F (V) is generated. measurements are taken.

表面がシリコン等の半導体又は導電体の場合には、この
時の測定値が小さいく、帯電解除の必要のないことがわ
かる。帯電のある場合にはこの時の値が一定値以上にな
るので、消去電荷の発生、つまり帯電解除の操作を行な
う。まず吸着時の電圧■0と逆極性ノttHEVx (
I vll < lVo l)ヲff1llj 4 ト
5の間に所定時間発生させた後、再びO■に戻し、時間
t1において剥離力F(V)をPlとして測定する。次
に電圧■1よりも絶対値の大きい電圧■2を所定時間発
生させて再びO■に戻し、時間t2において剥離力F(
V)をP2として測定する。このようにして電圧■。に
対し逆極性で順次増大する電圧を加えてはO■に戻して
剥P1f力F (V )を測定していくと、逆極性の電
圧(逆電圧)と剥離力P(V)の関係は第3図(b)の
ような特性になる。この特性からF(V)の最小値P、
を与える逆電圧■フの値がわかるので、チャッキング制
御部15はこの値を記憶する。このウェハに対しては最
小値P、をを通過した後に電圧v8の印加が組子すると
帯電解除を終えたことになる。同一の製造プロセスの同
一種類(同一ロット内)の他のウェハに対しては、帯電
解除の為の適正電圧の測定を行なう必要はなく、第4図
に示ずように、吸着時のm圧■oの発生を綜えただちに
記憶されている電圧値■フを加えた後Ovに戻せばよい
。その印加時間は、第3図(a)の電圧v7  の印加
時間とほぼ等しく定められている。
When the surface is a semiconductor such as silicon or a conductor, the measured value at this time is small, indicating that there is no need to release the charge. If there is a charge, the value at this time will exceed a certain value, so an operation to generate an erase charge, that is, to release the charge, is performed. First, the voltage at the time of adsorption ■0 and the opposite polarity nottHEVx (
After the peeling force is generated for a predetermined period of time between I vll < lVo l) and 5, the peeling force F (V) is measured as Pl at time t1. Next, voltage ■2, which has a larger absolute value than voltage ■1, is generated for a predetermined period of time and returned to O■, and at time t2, the peeling force F (
V) is measured as P2. In this way the voltage ■. By applying increasing voltages with opposite polarity and returning to O■ and measuring the peeling P1f force F (V), the relationship between the voltage of opposite polarity (reverse voltage) and the peeling force P (V) is The characteristics are as shown in FIG. 3(b). From this characteristic, the minimum value P of F(V),
Since the value of the reverse voltage {circle around (2)} that gives the voltage is known, the chucking control section 15 stores this value. When the voltage v8 is applied to this wafer after passing the minimum value P, it means that the electrification has been released. For other wafers of the same type (within the same lot) made in the same manufacturing process, there is no need to measure the appropriate voltage for charge release, and as shown in Figure 4, the m pressure during adsorption is It is only necessary to add the stored voltage value ■f immediately after the generation of ■o, and then return it to Ov. The application time is determined to be approximately equal to the application time of voltage v7 in FIG. 3(a).

このように、同一ロット内のウェハな多数処理する場合
、1枚目のウェハのみについてはがし力F (V、 )
を測定すればよく、それ以降のウェハについては、記憶
された適正電圧に基づいて極めて高速に帯電除去するこ
とができる。
In this way, when processing a large number of wafers in the same lot, the peeling force F (V, ) is applied to only the first wafer.
, and subsequent wafers can be removed from charge at an extremely high speed based on the memorized appropriate voltage.

尚、第1図において、電圧発生部10と電極4゜5の間
に直列接続された抵抗11は、ウェハ1の吸着時あるい
は取りはずし時の応答性(帯行の供給天ピード)を定め
るものである。また電極4゜5にウェハ1を載置した状
態は、電気的にコンデンサと等価であるから、抵抗11
とこのコンデンサとの直列接続は、いわゆる時定数回路
を形成する。そこで吸着させる時には抵抗11の値を小
さくシ、取りはずすときには吸着時よりも抵抗11の値
を大きくするようにしてもよい。このようにすると、ウ
ェハ1の吸着は速やかに行ブjわれ、かつ取りはすしの
際、第3ffl(a)の如く、吸着力の最小値を測定す
るための逆電圧印加の制御が厳しくならない利点がある
。具体的には逆電圧を印加する時間が極端に短くならな
いこと等である。
In FIG. 1, a resistor 11 connected in series between the voltage generator 10 and the electrode 4.5 determines the responsiveness (the feeding speed of the banding line) when the wafer 1 is attracted or removed. be. Also, since the state in which the wafer 1 is placed on the electrode 4.5 is electrically equivalent to a capacitor, the resistance 11
The series connection of this and this capacitor forms a so-called time constant circuit. Therefore, the value of the resistor 11 may be set small when it is to be attracted, and the value of the resistor 11 may be set to be larger when it is to be removed than when it is attracted. In this way, the wafer 1 can be quickly attracted and removed, and when removing the wafer 1, the control of applying a reverse voltage to measure the minimum value of the attraction force will not be strict, as shown in 3rd ffl (a). There are advantages. Specifically, the time for applying the reverse voltage should not be extremely short.

このため、吸着力の最小値が、再現性よく、かつ正確に
測定で゛きるようになる。
Therefore, the minimum value of the adsorption force can be measured accurately and reproducibly.

以上のように本発明によれば、静電吸着後の対象物とし
てのウェハの帯電を解除して、ウエノ・が吸着固定部と
離れ易くできるだけでなく、ウエノ1と他の導電体との
間に働く吸引力も減少さ七:ることかできる。また本発
明の実施例によれば、剥離力に上限を決めて加えること
から不必要な応力を半導体ウェハに与えることがなくな
り、応力による結晶欠陥の発生を抑えることかできると
いう利点がある。
As described above, according to the present invention, the charge on the wafer as a target object after electrostatic adsorption can be released, and the wafer can not only be easily separated from the adsorption/fixation part, but also be able to separate the wafer 1 and other conductive materials. The suction force that acts on it also decreases. Further, according to the embodiments of the present invention, since an upper limit is set for applying the peeling force, unnecessary stress is not applied to the semiconductor wafer, and there is an advantage that generation of crystal defects due to stress can be suppressed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例を示す機能ブロックを雄側した
断面図、第2図(a)は剥離力発生部の剥離力特性線図
、第2図(b)は位置検出器σ〕特性線図、第6図(a
)は電圧発生部の動作波形を示すタイムチャート図、第
6図(b)は消去電荷発生時の514H離力と逆電圧と
の関係を示す特性線図、第4図は別の例の電圧発生部の
動作波形を示すタイムチャート図である。 1・・・シリコンウエノ、、4 、5・・・電極(吸着
台)、4a、5a・・・絶縁層、10・・・電圧発生部
(消去電荷発生手段)、12・・・偏位部材、13・・
・剥離力発生部、14・・・位置検出器、15・・・チ
ャッキング制御部。 代理人  木 村 三 朗 第3図 才4図 129−
FIG. 1 is a sectional view of a functional block showing an embodiment of the present invention viewed from the male side, FIG. 2(a) is a peeling force characteristic diagram of the peeling force generating part, and FIG. 2(b) is a position detector σ] Characteristic diagram, Figure 6 (a
) is a time chart showing the operating waveform of the voltage generator, FIG. 6(b) is a characteristic line showing the relationship between 514H separation force and reverse voltage when erase charge is generated, and FIG. 4 is a voltage diagram of another example. FIG. 6 is a time chart diagram showing operation waveforms of the generator. DESCRIPTION OF SYMBOLS 1... Silicon Ueno, 4, 5... Electrode (suction table), 4a, 5a... Insulating layer, 10... Voltage generating part (erase charge generating means), 12... Deflection member , 13...
- Peeling force generating section, 14... position detector, 15... chucking control section. Agent Sanro Kimura Figure 3 Figure 4 Figure 129-

Claims (3)

【特許請求の範囲】[Claims] (1)導電体又は半導体等の対象物を載置して静電吸着
する吸着台と、吸着された対象物の吸着力を計測する測
定手段と、対象物の帯電前を消去するように前記測定手
段の計測値に応じた電荷量の電荷を前記吸着台に発生さ
せる消去電荷発生手段とを備え、対象物を前記吸着台か
ら取りはずす際に吸着力を略零にするようにしたことを
特徴とする静電吸着装置。
(1) A suction table on which an object such as a conductor or a semiconductor is placed and electrostatically adsorbed; a measuring means for measuring the adsorption force of the adsorbed object; and erase charge generation means for generating an electric charge on the suction table in an amount corresponding to the measured value of the measuring means, so that the suction force is reduced to approximately zero when the object is removed from the suction table. Electrostatic adsorption device.
(2)前記測定手段は、対象物に当接して該対象物に前
記吸着台からの剥離力を吸着力として検知する剥離力発
生手段を具備し、該剥離力発生手段の剥離力は対象物を
破損しない大きさに制限されていることを特徴とする特
許請求の範囲第1項記載の装置。
(2) The measuring means includes a peeling force generating means that comes into contact with the target object and detects the peeling force from the suction table as an adsorption force on the target object, and the peeling force of the peeling force generating means is applied to the target object. 2. The device according to claim 1, wherein the device is limited in size so as not to damage the device.
(3)  前記消去電荷発生手段は、吸着時とは逆極性
でかつ絶対値が順次大きくなる逆電圧を断続的に前記吸
着台に印加すると共に、該逆電圧の印加後、前記料量(
力発生手段によって剥離力を検知することを順次繰返し
、検知された剥離力が最小となったときの逆電圧値を、
吸着力を略零にするための電圧とすることを特徴とする
特許請求の範囲第2項記載の装置。
(3) The erasing charge generating means intermittently applies a reverse voltage to the suction table whose polarity is opposite to that at the time of suction and whose absolute value increases sequentially, and after applying the reverse voltage, the amount of the charge (
Detecting the peeling force using the force generating means is repeated sequentially, and the reverse voltage value when the detected peeling force becomes the minimum is calculated as follows:
3. The device according to claim 2, wherein the voltage is set to make the adsorption force approximately zero.
JP57177518A 1982-10-12 1982-10-12 Electrostatic attracter Granted JPS5967629A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57177518A JPS5967629A (en) 1982-10-12 1982-10-12 Electrostatic attracter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57177518A JPS5967629A (en) 1982-10-12 1982-10-12 Electrostatic attracter

Publications (2)

Publication Number Publication Date
JPS5967629A true JPS5967629A (en) 1984-04-17
JPH0263304B2 JPH0263304B2 (en) 1990-12-27

Family

ID=16032310

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57177518A Granted JPS5967629A (en) 1982-10-12 1982-10-12 Electrostatic attracter

Country Status (1)

Country Link
JP (1) JPS5967629A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01227454A (en) * 1988-03-08 1989-09-11 Nippon Telegr & Teleph Corp <Ntt> Electrostatic chuck
JPH0496221A (en) * 1990-08-03 1992-03-27 Matsushita Electric Ind Co Ltd Device and method for manufacturing semiconductor
JPH04213854A (en) * 1990-12-10 1992-08-04 Fujitsu Ltd Electrostatic suction device
JPH04247639A (en) * 1991-02-04 1992-09-03 Fujitsu Ltd Method of sucking and separating wafer by electrostatic chuck
US5350428A (en) * 1993-06-17 1994-09-27 Vlsi Technology, Inc. Electrostatic apparatus and method for removing particles from semiconductor wafers
US6140213A (en) * 1993-03-30 2000-10-31 Sony Corporation Semiconductor wafer and method of manufacturing same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014107382A (en) * 2012-11-27 2014-06-09 Fuji Electric Co Ltd Detachment method of semiconductor substrate

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01227454A (en) * 1988-03-08 1989-09-11 Nippon Telegr & Teleph Corp <Ntt> Electrostatic chuck
JPH0496221A (en) * 1990-08-03 1992-03-27 Matsushita Electric Ind Co Ltd Device and method for manufacturing semiconductor
JPH04213854A (en) * 1990-12-10 1992-08-04 Fujitsu Ltd Electrostatic suction device
JP2574066B2 (en) * 1990-12-10 1997-01-22 富士通株式会社 Electrostatic suction device
JPH04247639A (en) * 1991-02-04 1992-09-03 Fujitsu Ltd Method of sucking and separating wafer by electrostatic chuck
JP2576294B2 (en) * 1991-02-04 1997-01-29 富士通株式会社 Wafer suction / release method for electrostatic chuck
US6140213A (en) * 1993-03-30 2000-10-31 Sony Corporation Semiconductor wafer and method of manufacturing same
US5350428A (en) * 1993-06-17 1994-09-27 Vlsi Technology, Inc. Electrostatic apparatus and method for removing particles from semiconductor wafers

Also Published As

Publication number Publication date
JPH0263304B2 (en) 1990-12-27

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