JPS596581A - Semiconductor nonvolatile memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor nonvolatile memory device capable of electrically writing and erasing information.

As this type of semiconductor non-volatile memory device, a floating gate type EEPROM (Electric
ally Erasable and Program
ReadOnly Memory) and so-called MNOS (Metal N1tridOxide)
There is a Sem1 conductor type gEFROM, which has been attracting a lot of attention in recent years.

However, these EEFROMs are all FAMO8 (Floating G
ate Avalanche Injection MO
S) 9gFROM (Erasab
le and Programmable Read O
(nlyMemory), it is irradiated with ultraviolet rays or light with wavelengths close to the ultraviolet range (hereinafter simply referred to as ultraviolet rays). Therefore, write and read tests in the quefer state after manufacturing the quefer should be conducted at least to suppress ultraviolet rays. The drawback is that you have to do it.

Furthermore, the IC package of the conventional FJROM (FJ) ROM, which is erasable by ultraviolet rays, is equipped with a window made of ultraviolet-transparent glass, etc., and is configured so that all information on the chip is erased by irradiating ultraviolet rays through this window. On the other hand, the above-mentioned Yorina E
gFROM does not have such a window and has a structure in which the chip is wrapped in an insulating material such as plastic or ceramic, but in the future it will be possible to use ultraviolet irradiation, which has several times better information retention performance than EEPROM. Elimination type FAMO
8 memory and EEPR that allows information to be easily erased electrically
If you try to use OM in combination on the same chip, if you try to erase the FAMO8 memory by providing a window for UV irradiation, the FJCPROM will always be erased at the same time, so it is not always possible to take full advantage of the characteristics of both. I can't use it.

This invention was made in view of the above-mentioned circumstances, and its purpose is to provide a floating gate type EEPROM or MNO8 type FR which can be electrically written and erased.
An object of the present invention is to provide a semiconductor nonvolatile memory device that can store information regardless of irradiation with ultraviolet rays in OM.

In order to achieve such an object, the present invention includes at least one of the memory transistors arranged in a matrix wrapped in a shielding film that does not transmit ultraviolet rays. DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following - the invention will be explained in detail with the aid of an exemplary embodiment shown.

FIG. 1 is a side sectional view showing an example of a memory cell constituting a semiconductor nonvolatile memory device according to the present invention. This example shows a configuration example of a memory cell of a floating gate type n-channel EEPROM, and uses a p-type silicon substrate (
1), an n-type drain impurity diffusion region (hereinafter referred to as drain) (2) and an n-type source impurity diffusion region (hereinafter referred to as source) (3) formed at a predetermined interval from each other on the main surface of this substrate (1). , the sio film (4) formed on these surfaces, and the inside of the 5iOIl film (4) from above the drain (2) to the substrate (1) between the drain (2) and the source (3). Source through the top (3)
A floating gate conductor layer (hereinafter referred to as floating gate) (5) buried so as to reach above, and a tunnel k between the end of the floating gate (5) on the drain (2) side and the drain (2). 131Qfi film (6), 5ios film (
4) A control gate conductor layer (hereinafter referred to as control gate) (7) buried above the floating gate (5) and a barrier film made of a substance that blocks ultraviolet rays (8). It consists of (9). In addition, the drain (
2)l! Tunnel Sin between Yu Gate (5)! film(
6), whose film thickness is the same as that of the drain (2) and the floating gate (
5) 10 to 30 to allow a tunnel phenomenon to occur between
At the same time, the thickness of the 8103 film (4) directly under the floating gate (5) other than this portion is set to 500 A or more to prevent the tunneling phenomenon.

Further, the control gate (7) and the floating gate (5) are spaced apart from each other so that a tunnel phenomenon does not occur between them.

In the above configuration, charging the floating gate (5) with electrons is called writing, and releasing electrons from the floating gate (5) is called erasing.

Therefore, first, write to the drain (2), source (3)
) and the p-type silicon substrate (1) are grounded, and the tunnel 8
10! This is done by applying a positive voltage to the control gate (7) with respect to the substrate (1) so as to generate an electric field of the magnitude necessary to cause tunneling in the membrane (6). That is, by applying such a voltage, electrons tunnel 5 tons from the substrate (1) due to the tunneling phenomenon.
e6) and are injected into the floating gate (5), and the floating gate (5) is charged by the injected electrons to complete writing. Since the floating gate (5) is surrounded by the SiO2 film (4), the electrons that have charged the floating gate (5) remain in the floating gate even after the positive voltage applied to the control gate (7) is removed. (5) is maintained.

Next, electrical erasure is performed by controlling the control gate (7), the source (3)
and the p-type silicon substrate (1) are grounded, and the tunnel S1
0! This is done by applying a positive voltage to the drain (2) with respect to the substrate (1) so as to generate an electric field large enough to cause a tunneling phenomenon in the film (6). That is, by applying such a voltage ζ, an electric field is generated in the tunnel 5ins film (6) in the opposite direction to that at the time of writing, and the electrons accumulated in the floating gate (5) are transferred to the floating gate (5). ) through the tunnel 810g film (6) through the drain (2) and the substrate (1).
is released to complete the erasure.

Also, reading the written information is done using the floating gate (5).
The control gate (7
) changes in the threshold voltage. That is, depending on the on-state and off-state of the current flowing between the drain (2) and source (3) based on this change in voltage, a logic signal of "1'°" and "0" can be obtained.

In this way, electrical writing, reading and erasing of information are performed in the same manner as in the prior art.

However, even if this is irradiated with ultraviolet rays (8), the ultraviolet rays (8) are blocked by the shielding film (9) and do not reach the floating gate (5). Charge is held stably. That is, unlike conventional methods, information is not erased by unexpected or intentional irradiation with ultraviolet light.

The material constituting the shielding film (9) may be a conductive material such as molybdenum or an insulating material, as long as it shields ultraviolet rays.For example, as shown in FIG. It is covered with a barrier film (9a) consisting of a p-type silicon substrate (
A barrier film (9b) made of an insulating material that blocks ultraviolet rays (8) may be interposed on the contact surface with 1). By interposing the insulating shielding film (9b) in this way, it is possible to avoid the possibility that current will flow between the substrate (1) and the conductive shielding film (9a), causing noise. Next, FIG. 3 is a block diagram showing an embodiment of the present invention in which the same semiconductor chip is equipped with a memory in which an EEFROM that cannot be erased by ultraviolet irradiation and an EFROM that can be erased by ultraviolet rays as described above are mixed. be.

In the figure, the memory (11) is 11 of AO-AIO.
There is a book address input and data output terminal (12)
Since there is only one, it has a storage capacity of 2" x 1 = 2048 bits. The signal given as the address input signal of AO-Ale is sent to the row address decoder (14) and It is decoded by a column address decoder (15) to select a predetermined memory address with a capacity of 1 bit in the memory (11).

The memory (11) consisting of memory cell transistors arranged in a matrix is an FA that can be erased by ultraviolet irradiation.
MO8) The first memory area (ll
a) and an EEF that cannot be erased by ultraviolet irradiation according to the invention
A second memory area (llb) (shaded area) consisting of ROM, and both areas have different column addresses. Therefore, the column address input signal “
By setting it to "H" or "L", either one of the memory areas can be selected.

The first memory area (lla) is connected to a read/write control circuit (16) including a sense amplifier, and the read/write mode is selected by the read/write signal input to the read/write signal terminal (17). be done. In addition, a data input/output circuit (18
) is connected to the data input/output terminal (12).

Further, the second memory area (llb) is connected to a data input/output terminal (12) via a read/write control circuit (16) and a data input/output circuit (18), and also Control circuit (1
9) to an erase signal terminal (20) and a read/write signal terminal (17).

Next, to explain the operation of the above configuration, first, address inputs Ao-Ale are set, and data input/output terminals (
By inputting arbitrary data "1" or "0" from 12) and setting the read/write signal to write mode, arbitrary data "0" or "1" is written to a predetermined memory address.

At the time of reading, by setting the address input AO-Ale and setting the read/write signal to read mode, a “1” or “0” signal indicating the data written from the predetermined memory address is sent to the sense amplifier and output. Data input/output terminal (12) via buffer
is output to.

Next, for the second memory area (11b) consisting of EEFROM, an erase signal is applied to the erase signal terminal (20) and the erase/read/write control circuit (19) is erased.
) can be performed electrically. FAMO8) The first memory area (lla) consisting of a run transistor can be erased by irradiating it with ultraviolet rays, but at this time the second memory area (llb),
The information written on the film is not erased and is stored because the film resists ultraviolet rays.

Therefore, when a non-volatile storage device with the above structure is mounted on a system board, information that does not require frequent rewriting is stored in the FAMO8 memory area, which has retention characteristics several times better than ggFROM, as described above. Information that is frequently rewritten can be stored in the ggFROM area and rewritten using electrical signals while mounted on the system board.

Furthermore, information in the FAMOS memory area is erased by irradiation with ultraviolet light, but information in the EEFROM area is not erased by ultraviolet light. Therefore, when erasing is performed by irradiating ultraviolet rays, it is possible to save information that does not want to be erased by storing it in the EEPROM area in advance.

In the above-described embodiment, the memory transistors are arranged in a matrix of 10 rows and 2 columns, and the FAMOS memory area that can be erased with ultraviolet light and the EEFROM area that cannot be erased with ultraviolet light can be selected by the column address input signal of the AIO. The present invention is not limited to this, and it goes without saying that selection can be made using any row or column address signal.

FIG. 4 is a block diagram showing another embodiment of the invention. That is, in this example, Memo I) (21) is written as ・-\
-゛Data input/output terminals (22a) and (22b) respectively
1, corresponding to.

and a first memory area (2) connected to the data input/output terminal (22a) via the data input/output circuit (24a).
A second memory area (22b) is connected to a data input/output terminal (22b) via a sense amplifier (23b) and a data input/output circuit (24b) using a FAMO8) transistor that can erase 1a) by ultraviolet irradiation. 21b) EEFR in which (shaded area) is made unerasable by providing a UV blocking film
It is composed of OM, and the user can write and read each piece of information into each memory area from each input/output terminal by dividing it into υ categories according to their different characteristics.

Note that the above-described embodiment is an example having two data input/output terminals and two memory areas corresponding to each data input/output terminal, but when providing a larger number of input/output terminals and memory areas corresponding to the data input/output terminals, one of them Of course, any of the plurality of memory areas may be constituted by an EEPROM that cannot be erased by ultraviolet rays, and the remaining memory areas may be constituted by FAMO8) run transistors which can be erased by ultraviolet rays.

Furthermore, in the above embodiment, the floating gate type EEFECM
Although the present invention has been described only for the case where an MNOS-type IJPROM is used, the present invention is not limited to this. An example of a memory cell is shown below.
In the same figure, p
A source (3
) Thin tunnel 81 of about 10 to 50A extending above
(A thick nitride film (32) of about 300 to 600 A and a gate (33) are buried through M[6), but the tunnel 5ios film (6), nitride film (32) and gate (33) are Tunnel 5103 membrane in Figure 1 (
6) and floating gate (5) and control gate (7)
corresponds to In addition, the same symbols as in FIG. 1, such as the membrane (9), indicate the same parts, and the functions are exactly the same as those in FIG. 1. Similarly, when the insulation film is composed of a conductive shielding film (9!L) and an insulating shielding film (9b) as shown in FIG. 6, the same thing as shown in FIG. Indicates the action and effect of

As explained above, according to the present invention, in a ggFROM that can be electrically written and erased, at least that part is covered with a barrier film that does not transmit ultraviolet rays. This is effective in improving reliability because information can be protected from unnecessary UV irradiation.

For example, by combining FAMO8 memory, which has excellent retention characteristics and can be erased by ultraviolet rays, and configuring these on the same semiconductor substrate, a part of the memory area on the substrate can be intentionally irradiated with ultraviolet rays. This has the advantage that it can be used in a variety of ways, since other areas can be erased electrically and not erased by ultraviolet rays.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing an example of a memory cell constituting a semiconductor nonvolatile memory device according to the present invention, FIG. 2 is a cross-sectional view showing another example, and FIG. 3 i is a block diagram showing an embodiment of the present invention. 4 are block diagrams showing other embodiments, and FIGS. 5 and 6 are sectional views showing other configuration examples of the memory cell. (1)...p-type silicon substrate, (4)...5i
ll film, (5)... floating gate, (6)... tunnel 8102 film, (7)... control gate, (8)
...Ultraviolet light, (9), (9a), (9b)...
...Syahei membrane, (11), (21)...Memory, (lla). (21a)...First memory area that can be erased by ultraviolet rays, (llb), (21b)...Second memory area that cannot be erased by ultraviolet rays, (12), (2
2a). (22b)...Data input/output circuit, (32)...
・Nitride film, (33)...gate, AO-AIO...
...Address input signal. Agent Makoto Kuzuno - -35'

Claims (6)

[Claims] (1) In a semiconductor nonvolatile memory device equipped with a memory element formed by arranging field effect memory transistors in a matrix in which information can be electrically written and erased,
A semiconductor nonvolatile I-ratio storage device characterized in that at least one field-effect memory transistor is wrapped in a barrier film that does not transmit ultraviolet rays. (2) Claim 1, characterized in that the field effect memory transistor is a floating gate type field effect memory transistor comprising a floating gate capable of storing charge and a control gate insulated on a semiconductor substrate. The semiconductor non-volatile memory device described in 1. (3) Claim 1, characterized in that the field effect transistor is an MNOS type field effect memory transistor comprising a silicon nitride film formed on a semiconductor substrate via a thin silicon oxide film. The semiconductor nonvolatile memory device described above. (4) Field-effect memory transistors that can electrically write and erase information and that cannot be erased by ultraviolet irradiation by being wrapped in a barrier film that does not transmit ultraviolet rays; 1. A semiconductor nonvolatile memory device comprising a memory element in which 77MO8 type field effect memory transistors that can be erased only are mixed and arranged in a matrix on the same semiconductor substrate. (5) Field effect memory transistors that cannot be erased by ultraviolet irradiation and 77MO8 type field effect memory transistors are arranged in memory areas each having a specific row or column address, and a specific address input signal is 5. The semiconductor nonvolatile memory device according to claim 4, wherein one of the transistor groups can be selected by. (6) A field effect memory transistor that cannot be erased by ultraviolet irradiation and a 77MO8 type field effect memory transistor are arranged in memory areas that correspond to specific data terminals, respectively. A semiconductor nonvolatile memory device according to claim 4.