JPS5965377A - Method and device for address control - Google Patents

Abstract

PURPOSE:To decrease the number of steps and at the same time to reduce the circuit scale when the signal which uses data periodically and repetitively is processed by calculating the present address number by a desired equation and by means of the maximum and minimum address numbers, a pre-address number and an increment degree or a decrement degree. CONSTITUTION:The minimum and maximum address numbers are defined as A0 and An-1 respectively in a storage region, and pre-address number is defined as D0 with increment and decrement degree set at I1 and I2 respectively. In such a case, the present address numbers D1 (increment) and D2 (decrement) are obtained from an equation (1) and (2) respectively. In other words, the increment degree I1 (I1>An-1D0), the circulating period n(n=2I<-1>), A0 and An-1 are set to registers R11, R12, R13, R14 respectively, for example, to start the 1st period. As a result, the R13 is set to D0 and then D0+I1 with addition of the I1 to obtain a product with the R12 through an AND. In such a way, the signal processing is accelerated along with the reduction of the circuit scale.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention uses a plurality of data cyclically and repeatedly to perform product or sum operations, sampling, encoding,
The present invention relates to an address control method and device used to specify the address of a storage device that accesses data when signal processing such as decoding is performed at high speed.

FIG. 1 is a principle diagram of a conventional address control method, in which an address signal bO to bH-1 consisting of □□□H bits is applied to an address input of a memory device MM from an address control device ADC, and this address signal Data is accessed in m storage areas corresponding to , and various signal processing is performed based on the accessed data.

In this case, the H-bit address signal bO to bH-1
The number m of storage areas specified by m=: 2H−
It becomes 1.

In addition, linear predictive coding is an example of this type of signal processing. things are being done.

FIG. 2 is a signal flow diagram in linear predictive coding, in which the input signal xt and the predicted signal are supplied to the subtracter SUB,
The residual signal elt at time t is calculated by the following equation.

@ j”XtXtll @ @ a * e * (1
) is given to the encoder C, becomes the encoded residual signal rt, and is sent to the output OUT,
At the same time, it is applied to the adder AD, and a computation of the following equation is performed with the prediction signal xt to obtain the encoder Δ signal xt.

Δ ~ to xt = xt-4-et e fist... (2) △ Also, the encoded signal xt is given to the linear predictor P, and this
, n-th linear prediction coefficients α1 to αn△
Δ and n encoded signals Xt-1 to XI- in the past.

The calculation of the following equation is performed to obtain the prediction signal xt.

In the above-mentioned linear predictive coding process, in order to derive the predictive signal Xt, the linear predictive coefficient α of Δ in the memory device and the encoded signal X1 . , -) c is performed, and at this time, the encoded signal △ As past data becomes unnecessary one after another, the addressing for the encoded signal xt-k is updated while changing the starting address number one by one, and incrementing is repeated n times. .

However, in this method, the starting address number continues to increase, and for the purpose of minimizing the capacity of the memory device, the first
When the contents of a memory device are shown in the table, it is generally an operation of storing data representing n encoded signals at n addresses and sequentially replacing unnecessary past data with new data. It is supposed to be carried out.

Table 1 Therefore, when specifying an address, it is necessary to increment the address number by one and to cycle the address specification by the period n. A control device was used.

The figure is a functional block diagram, and if addressing is to be performed in cycles n for a memory device having the nth address, an increment of 1 for the address number is set in register R1, and register R2 is , Set the initial address number O to Rs, set the highest address number in the addressing circulation area to register R4, set n-1 to register R5, and reset counters C1 and C2. The first period of operation is started.

Then, the initial address number of register R3 is
At D, it is added to the increment in register R1 to obtain the next address number, which is then given to register R3 via selector SEL, and its contents are updated.In order to repeat this operation, the increment from register R3 is added. Output OUT
gives an address number that increases by successive increments.

Further, the counter C2 is incremented by one each time the contents of the register R3 are updated, and the counter C2 is incremented by one each time the contents of the register R3 are updated.
-1, the comparator COMP2 sends out a coincidence output to operate the control circuit C0NT2, incrementing the counter C1 by one via a path not shown in the figure, and inputting the input of the selector SEL from the adder ADD. In order to switch to the output of counter C1, the contents of register R3 are updated by the contents of counter C1.

Note that, immediately after the contents of the register R3 are updated by the contents of the counter C1, the selector SEL selects the adder AD again.
Select the output of D.

Therefore, after the contents of the counter C1 indicating the first address number in the second period are given to the register R3, addition with increments is repeated using this as a reference, and as described above,
Sequentially increasing address numbers are sent.

Also, before the contents of counter C2 become equal to the contents table of register R5, that is, in the middle of the period, register R3
If the content of is equal to n-1 and is equal to the final address number of register R4, comparator COMP1 generates a match output, operates control circuit C0NTs, and transfers the input of selector SEL from adder ADD to the output of register R2. , the contents of register R3 are updated to the initial address number 0 of register R2.

Note that, immediately after the contents of the register R3 are updated by the contents of the register R2, the selector SEL selects the adder A again.
To select the output of DD, addition with the increment is repeated based on the initial address number, and the result is stored in register R3.
Sent from

Therefore, by repeating the above operations, a circulating address number for each cycle is generated, and this address number is used for linear predictive coding as shown in Table 2.

Table 2: In the first period when the contents of counter C1 is O, the contents of counter C2 match the address number, but in the second period when the contents of counter C1 is 1, the contents of counter C2 match. If the start address number is 1 and the end address number is 0, the start address number of each cycle is incremented by one each time the cycle period indicated by the contents of counter C1 increments. \increase, and the address number is increased in each cycle using this as a reference.

However, in the case of the configuration shown in FIG. 3, it is necessary to control the selector SEL by the comparator COMP1 and the control circuit C0NTt every time the address number reaches the final address number, which has the drawback of increasing the circuit scale. arise.

Note that if the above control is performed by software, the circuit scale will be small, but conditional jump instructions etc. will require a lot of programming time, and the time required to execute them will be large. This results in a drawback that it is impossible to perform linear predictive coding.

The present invention was made in view of the drawbacks of the conventional art.
b. The first and second aspects are to provide an address control method that generates a required address number through simple calculations.
This is a book whose third purpose is to provide an address control device that generates address numbers for circuits with a simple configuration.

FIG. 4 is a diagram illustrating the principle of the present invention. As shown in FIG. When specifying an address using address signals bO to bI (-1) consisting of H bits from the address control circuit ADC to the ME, the minimum address number of the storage area ME having the number of storage areas m=2"-" is set to AO1 maximum. If the address number is Ayl-1 (Tasoshi n-2), as shown in Figure (b), if address number An-1 is increased by one, the address number will not become An. Naturally AO
In other words, if the address number is increased sequentially, the address number will rotate at a cycle n.

Incidentally, regardless of the amount of increase, the circulation of address numbers remains the same.

FIG. 5 is a diagram showing a linear expansion of the circulation of address numbers in the storage area MEK of FIG. 4(b).
) shows a case in which circulation is performed by addition, and (b) shows a case in which circulation is performed by subtraction, where the minimum address number of the storage area is Ao, the maximum address number is An-1, and the previous address number is Do. (Tasoshi AO=-〇≦An-1),
If the current address number obtained by the calculation is Dl or D2 (D AO(D 1 <An-,.

Or Ao(D2(AH-x), the amount of increase is 11 (parable 11>An-1-1)o), and the amount of decrease is I2 (Tax I2>DO-Ao)! In D, (,), if you add the increment amount 11 to the previous address number 1)o, you get DO+11, which becomes the current address number Dl, but the increment amount 11 includes the previous address number DO and the maximum address number. The difference An-1-DO from An-t and the difference An-f-AO between the maximum address number An-1 and the minimum address number AO caused by going through the storage area once.
It's great that it's included! l', DO+I 1 and the maximum address number Al-t immediately before this and Q test 1
l-(AH-x-AO)-(An-1-Do).

Therefore, the difference between the minimum address number Ao and the current address number Di is also I1-(An-1-Ao)-(An-t
-1)-o) and the current address number D1 is such that this difference is added to the minimum address number AO, so that the number of cycles is k(t'Nl, 1Ω, 1. 2
), then the following formula generally holds true.

DI=AO+[I 1-k(An-1-AO)-(An
-1-DO)]...@-. (4) Also, in (b), if you add the previous address number DO/-5 decrease ■2, it becomes DO+I2, which becomes the current address number D2. , the decrease amount I2 includes the difference between the previous address number DO and the minimum address number, DO-Aa, and the difference An between the maximum address number An-1 and the minimum address number AO, which is generated by one cycle of the storage area. −
1-AO is included, and the difference between ])o+I2 and the maximum address number An-1 immediately after this is I2-(A
n-1-AD)-(Do-Ao).

Therefore, the difference between the maximum address number An-1 and the current address number D2 is also I2-(An-1-Ao)-(DO-
AO), the current address number D2 is the difference obtained by subtracting this difference from the maximum address number, so the number of cycles is set to k (=0.1.2...). For example, the following formula generally holds.

1) 241-1-(I2-k(An-1-Ao)-(1
)o-AO))1]e...(5) Therefore, if the calculation of equation (4) or equation (5) is realized by an arithmetic circuit or software, the current address number D1 or p2 can be sequentially obtained. I can do it.

Ru.

FIG. 6 is a functional block diagram of an address control device incorporating the idea shown in FIG. The output of this circuit is applied to one input of the AND circuit counter, and the output of the same circuit MΦ is applied to the second register R13 via one input of the selector SEL.

Further, the output of the register R1a is sent to the output OUT, and is also given to the other input of the adder ADD.
The other input of Φ to the AND circuit is a third register R12.
The basic circuit is constructed from these outputs.

Note that the output of the first counter C1 is given to the other input of the selector SEL, while the output of the fourth register R1
4 and a second counter C2 are provided, and their outputs are given to the inner inputs of a comparator COMP, and when the inner inputs match, the comparator COMP produces a match output, thereby operating the control circuit C0NT. , the selector SEL switches from the AND circuit AND to the output of the counter C1.

In this case, in order to obtain from the output OUT an address number that circulates every period n necessary for linear predictive encoding, set an increment of 1 corresponding to the increase amount 1 or the decrease amount I2 in the register R11, and set the register R1z has a circulation period n(ta':
L n = 21-1), the lower bits are all 11'', the rest is 10' data, the initial address number O is set in register R13, and the maximum address number n is set in register R14. After setting data indicating -1 and resetting the counters C1 and C2, the first period of operation is started.

Then, the contents of register R13 are the previous address number Do.
The increment amount is added to the adder ADD as DO+
11 or DO+I2, and the logical product circuit AND takes the logical product with each bit indicating the lower X'1'', and the current address number D1 becomes D2. After updating the contents of the register R13 via the selector SEL, the output OU
It is sent from T as the current address number D1i or D2.

Further, the counter C2 is incremented by one each time the contents of the register R13 are updated, and when the contents of the counter C2 become equal to the contents of the register R14, the comparator COMP
sends out a coincidence output to operate the control circuit C0NT, incrementing the counter C1 one by one through a path not shown in the figure, and controlling the selector SEL to select the output of the counter C1.

Therefore, the contents of register R13 are updated by the contents of counter Cs, and this becomes the starting address number in the second cycle.

However, immediately after the contents of the register R13 are updated according to the contents of the counter C1, the selector SEL selects the output of the AND circuit AND again. The current address number is sequentially increased and the above operation is repeated.

In addition, in FIG. 6, by passing the output of the adder ADD through the AND circuit AND and taking the AND with the contents of the register R12, the carry of the I-th bit from the lower order is ignored and automatically executed. , the minimum address number 0 is given to register R13.

Therefore, the register R4 required in FIG.
The comparator C0MPt, control circuit C0NTt, register R2, etc. are not required, and the address numbers for linear predictive encoding shown in Table 2 can be generated at high speed with a simple configuration.

In addition, by using equation (4) or (5), it is possible to obtain the address number for linear predictive coding through simple calculations, so the calculation time is shortened and the required address number can be obtained quickly. can be generated.

For example, in FIG. 6, if linear predictive coding is performed only once, the selector SEL may be deleted, and the register R14, counter C1°C2, and comparator C
OMP and control circuit C0NT can be deleted.

As is clear from the above description, according to the present invention, when performing signal processing that uses data periodically and repeatedly,
While the number of program steps is reduced and high-speed processing is realized, the circuit scale of the control device is reduced, and the chip area is reduced when integrated circuits are integrated, resulting in significant effects in various digital signal processing devices.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of a conventional address control method, Fig. 2 is a signal flow diagram in linear predictive coding, Fig. 3 is a functional block diagram showing a conventional address control device, and Fig. 4 is a diagram of the present invention. FIG. 5 is a diagram illustrating the cycle of address numbers developed linearly, and FIG. 6 is a functional block diagram of an address control device showing an embodiment of the present invention. MM...Memory device, ME...4...Storage area, A
O...Minimum address, Ah-]...Maximum address, R11 to R1a...Register, ADD...
... Adder, AND-... Logical product circuit. Patent Applicant Masaki Yamakawa Agent, Nippon Telegraph and Telephone Public Corporation Figure 1 Figure 2 Figure 3 Figure 10 [LJT Figure 5 (0) (bl Figure 6 UT

Claims (3)

[Claims] (1) In an address control method in which the storage area of a memory device is used by specifying an address number, the minimum address number among the address numbers in the memory storage is set to AO1.
When the maximum address number is An-t, the previous address number is Do (Ta'f, L A o ≦ Do ≦ AH-t), and the amount of increase is Is (Tasoshi It) An-t → 0). ,
Current address number DI(Ao(Dl(An-t)
) to D 1=AO+(ll-k(An-1-A(+)-(A
nt-Do)) (Tasoshini=o, 1.2...). (2) In an address control method for saving a storage area of a memory device by specifying an address number, the address number among the address numbers in the storage area is set to 80,
When the maximum address number is An-1, the previous address number is Do (fLAo≦DO≦Ar1-1), and the amount of decrease is I2 (I2>DO-Ao), the current address number is D2(Tasoshi A O<D 2(An-1
) as Dz==An-t-(Iz-k(An-t-Ao)
-(Do-Ao) (Tay = o, 1.2,...
). (3) first and second registers, an adder to which the output of the first register is applied to one input, and an output of the adder to which the output of the adder is applied to one input, and an output of the second register; Address control characterized by comprising: an AND circuit to which is given to the other input; and a third register to which the output of the AND circuit is given and which gives its own output to the other input of the adder. Device.