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JPS595665A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS595665A
JPS595665A JP57113898A JP11389882A JPS595665A JP S595665 A JPS595665 A JP S595665A JP 57113898 A JP57113898 A JP 57113898A JP 11389882 A JP11389882 A JP 11389882A JP S595665 A JPS595665 A JP S595665A
Authority
JP
Japan
Prior art keywords
transistor
collector
emitter
circuit
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57113898A
Other languages
Japanese (ja)
Inventor
Hidenori Kitajima
秀則 北島
Kenichi Tonomura
健一 外村
Takashi Iizuka
孝 飯塚
Noriaki Oka
岡 則昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57113898A priority Critical patent/JPS595665A/en
Publication of JPS595665A publication Critical patent/JPS595665A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30Devices controlled by electric currents or voltages
    • H10D48/32Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H10D48/34Bipolar devices
    • H10D48/345Bipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions

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  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain an accurate output signal based on an input signal, by grounding an emitter, which is closest to each collector of each multiemitter transistor that is provided in the same direction, and supplying the input signal to the other emitter. CONSTITUTION:Four transistors Q11, Q12, Q13, and Q14 are formed. A Schottky barrier diode is formed between an N type epitaxial layer 3 and an aluminum layer 6. The bases of the transistors Q11, Q12, Q13, and Q14 are connected through internal resistances rb1, rb2, rb3, and rb4. A collector terminal C and each collector of the transistor Q11-Q14 are connected through internal resistances rc1, rc2, rc3, rc4, and rc5, and also connected to the cathode of the Schottky barrier diode through internal resistnaces r1 and r2. The collector terminal C is connected a load circuit. An emitter E14 of the transistor Q14 which is closest to the collector C, is grounded. An input signal is supplied to emitters E13, E12, and E11.

Description

【発明の詳細な説明】 本発明は、T T L (Tranetstor −T
ranele −tor LIogLc )回路に用い
て好適な半導体集積回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a TTL (Tranetstor-T
The present invention relates to a semiconductor integrated circuit suitable for use in a ranele-tor LIogLc) circuit.

TTL+回路の入力端には、第1図に示す如きショット
キーバリアダイオードkWするマルチエミッタトランジ
スタ(以下においてトランジスタという)Ql か多用
されている。上記トランジスタq1は、同一半導体基板
上に共通のペースと共通のコレクタとケ有する例えば4
個のトランジスタからm成される。そして、工εツタの
みが図ボのg+」< 11ω別に設けられているか、こ
のうち工iツタfaIk接萌し、他のエミッタE茸、J
!lj3 %  W4に入力招号紮供h6することがあ
る。
At the input end of the TTL+ circuit, a Schottky barrier diode kW multi-emitter transistor (hereinafter referred to as a transistor) Ql as shown in FIG. 1 is often used. The transistor q1 has, for example, four transistors having a common space and a common collector on the same semiconductor substrate.
It is made up of m transistors. Then, only the emitter ε ivy is provided separately for g+''
! lj3 % W4 may be given an input invitation h6.

上述のvOき使用方法の場合、本発明者の検討によれは
、工ごツタE、〜E4に供給される入力信号ケ同時にH
レベルからLレベルにした時、出力竜流工。Lにいわゆ
るひけが現われることが慣1明した。この現象は、人力
信号の立上り位It及びや下り位置において、瞬間的な
大電流となって現われる。この結果、TTLl路(図示
せず)の出力端に例えばラッチ回路を接続した場合、上
記ひげ、丁なわち瞬間的な大1!L流によってラッチ回
路が誤動作してしまう。なお、ラッチ回路としては、カ
ウンター回路、シフトレジスタ回路等がある。
In the case of the above-mentioned method of using VO, according to the studies of the present inventors, the input signals supplied to the workpieces E, to E4 are simultaneously
When going from level to L level, the output dragon flow technique. I have become accustomed to the appearance of so-called sink marks on L. This phenomenon appears as an instantaneous large current at the rising position It and slightly falling position of the human input signal. As a result, if, for example, a latch circuit is connected to the output end of the TTLl path (not shown), the above-mentioned whisker, that is, an instantaneous large 1! The latch circuit malfunctions due to the L current. Note that the latch circuit includes a counter circuit, a shift register circuit, and the like.

依って、本発明の目的とするところは、人力信号にもと
づき正確な出力信号が祷られる牛導体集槓回路を提供す
ることKある。
SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a cattle conductor collector circuit which can produce accurate output signals based on human input signals.

以下、第2図〜第61r参照して本発明の一実施例r述
べる。
Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 2 to 61r.

槙2図は、ショットキーバリアダイオード?Nするマル
チエミッタトランジスタQ+ の弄1曲回路とその構造
r示す半導体集積回路の要部の断面図である。
Is Maki 2 a Schottky barrier diode? 1 is a cross-sectional view of a main part of a semiconductor integrated circuit showing a circuit of a multi-emitter transistor Q+ and its structure.

1はP型サブストレート、2はN+埋込1−13はN型
エピタキシャル層、4はP型ベース拡散層、5a、5b
、5C15dはN+エミンp拡散層、6はアルミニウム
層、7は二酸化シリコン層である。上述のvOき構造の
半導体集積回路(切下において工0という)において、
図示の+71j@4個のトランジスタQ、11%  Q
txx  QCs、Q目が形成され、川にHgエピタキ
シャル層3とアルミニウム層6との間でショットキーバ
リアダイオードか形成される。この工うに構成されたI
Cは、回路記号として図示すると第1図の如きトランジ
スタQIになる。
1 is a P type substrate, 2 is an N+ buried layer 1-13 is an N type epitaxial layer, 4 is a P type base diffusion layer, 5a, 5b
, 5C15d is an N+ emine p diffusion layer, 6 is an aluminum layer, and 7 is a silicon dioxide layer. In the semiconductor integrated circuit of the above-mentioned vO structure (referred to as 0 in the cut),
+71j shown @ 4 transistors Q, 11% Q
txx QCs are formed, and a Schottky barrier diode is formed between the Hg epitaxial layer 3 and the aluminum layer 6. I configured this process
When C is illustrated as a circuit symbol, it becomes a transistor QI as shown in FIG.

そして、各トランジスタQz、Q目、Q+++、4口の
各ベースは、内部抵抗rbll  bl、r b 、、
r b 、を弁して接続され、コレクタ端子Cと各トラ
ンジスタQ目〜GL14 の各コレクタとは内部抵抗r
 o+、 。3、 。1、 。4、ro、を弁して接続
さ1% 史に内部抵抗rI%  rlを介してショット
千−バイアダイオードのカンードに接続されている。
The bases of each transistor Qz, Qth transistor, Q+++, and 4 transistors have internal resistances rbll bl, r b , ,
r b , and the collector terminal C and each collector of each transistor Q to GL14 have an internal resistance r
o+, . 3. 1. 4, ro is connected to the cand of the Schott 1,000-via diode through the internal resistance rI% rl.

なお、ショットキーバリアタイオードのアノードは、抵
抗(図示せず)を介して+voo市源に接続されるとと
もに、トランジスタQlのベースに接続はれる。fた、
コレクタ端子Cは負イ叶回路(図示せず)に接糸71芒
れる。
Note that the anode of the Schottky barrier diode is connected to the +voo source via a resistor (not shown), and is also connected to the base of the transistor Ql. F,
The collector terminal C is connected to a negative loop circuit (not shown) by 71 threads.

本実施例においては、コレクタCに一番近いトランジ7
り4口のエミッタBj I4  を接地し、エミッタ’
!’ l !1%  ’L l !、gt+に入力信号
を供給する。
In this embodiment, the transistor 7 closest to the collector C
Ground the four emitters Bj I4, and
! 'l! 1% 'L l! , gt+.

そして、本弁明渚の実験によれば、人力4g号をHレベ
ルからbレベルに変化した時、或い(・よLレベルから
Hレベルに変化した時、コレクタ自流に瞬間的に大電流
が流れなかった。
According to Honbenmei Nagisa's experiment, when the human power 4g changes from H level to B level, or from L level to H level, a large current momentarily flows through the collector current. There wasn't.

以上のνIJ@良好な実験結果は、下記の叩く理由づけ
られる。
The above νIJ@favorable experimental results can be explained as follows.

丁なわら、トランジスタQ14のベースにハ、内111
S姐抗r 〜r  を弁してペース屯流工、が供bI 
    b4 紺さlしる。このため、内部抵抗rbi〜r b 4に
はトランジスタQt4に飽和8ぜる之めの光分なベース
−流よりがυiuLることになり、dい44えればショ
ットキーバリアダイオードによるクランプ効果が小にな
る。そして、入力信号がHレベルからLレベルに変化し
た時、出力菟流工OLをドライブするのに必要なトラン
ジスタGL14のペース電流が得うレる。故に、トラン
ジスタQ目は、飽和領域から外づれることがなく、出力
車流工OLに瞬間的に大きな電流が流れない。
However, the base of the transistor Q14 is 111.
The pace tonryuko is provided bI with S 8 resistance r ~ r
b4 Dark blue color. For this reason, the internal resistance rbi~rb4 has a base current υiuL of the amount of light that saturates the transistor Qt4, and the clamping effect by the Schottky barrier diode is reduced if d44 become. Then, when the input signal changes from the H level to the L level, the pace current of the transistor GL14 necessary to drive the output circuit OL is obtained. Therefore, the Q-th transistor does not deviate from the saturation region, and a large current does not momentarily flow through the output flow circuit OL.

ちなみに、エミッタE目を接地しエミッタE目〜刊口に
入力信号を供給し、この入力信号をHレベルからLレベ
ルに変化させると、出力電流工ohに瞬間的に大電流が
現われた。この場合、トランジスタQ、のベースには、
内部抵抗rbIを弁してペースIII流よりが流れる。
By the way, when emitter E is grounded and an input signal is supplied to emitter E to the paper slot, and this input signal is changed from H level to L level, a large current momentarily appears in the output current oh. In this case, at the base of transistor Q,
Pace III flows through the internal resistance rbI.

ペース電流よりは、ショットキーバリアダイオードを流
れる電流を工8、出力電流を工OLとすると、 ■b:!:工s+Inr、/l’1rpQ口で法定され
る。丁なわち、トランジスタQ目のベースには、トラン
ジスタQ目を飽和させるためのベース電流よりしか流れ
ない。この状態で、人力1百号(5HレベルからLレベ
ルに変化させると、トランジスタQ511に流れていた
ベースtVi、 bWが減少して、そのコレクタ電流も
減少する。
From the pace current, if the current flowing through the Schottky barrier diode is 8, and the output current is OL, ■b:! :Eng s + Inr, /l'1rpQ mouth. In other words, only the base current for saturating the Qth transistor flows through the base of the Qth transistor. In this state, when the voltage is changed from the 5H level to the L level, the base tVi, bW flowing through the transistor Q511 decreases, and its collector current also decreases.

−力1 トランジスタQ11%  Ql1%  Q目に
6−ヌ亀流が流れることによって、各トランジスタqt
z〜Q目にコレクタ電流が流!tようとするが、ペース
電流が流gでからコレクタ電流が流2Lる寸でに遅延時
間がある。そして、トランジスタ9口のコレクタ電流を
l−とすると、■自〈■oLの関係になった時、このト
ランジスタQ目が飽オD領域から外づれてコレクタ電圧
が上昇する。仄いで、所定遅延時間後に、トランジスタ
Q1.〜Q14が動作してそれぞれにコレクタ電流が流
れ、トランジスタQ目も書び飽和領域になる。従って、
トランジスタQllが飽和領域から外づれ、再び飽和領
域になるまでの開で、出力電流工OLに変動が現われる
-force 1 Transistor Q11% Ql1% By the flow of the 6-N torque, each transistor qt
Collector current flows between z and Q points! However, there is a delay time from when the pace current reaches g to when the collector current starts to flow at 2L. If the collector current of the 9 transistors is 1-, then when the relationship ①<②oL is established, the transistor Q deviates from the saturated D region and the collector voltage increases. Then, after a predetermined delay time, transistor Q1. ~ Q14 operates and collector current flows in each, and the Qth transistor also writes and enters the saturation region. Therefore,
As the transistor Qll moves out of the saturation region and returns to the saturation region, a fluctuation appears in the output current OL.

ところか、本実施例に示すvl〈トランジスタQ、目の
エミッタfit4に接地し、エミッタ”11〜式8に人
力1汀号を供給し几場合、トランジスタ9口か飽和状態
から外づハることがない。従って、出力電流工OLが変
動することもない。
However, if the emitter fit4 of VL transistor Q shown in this embodiment is grounded and human power 1 is supplied to emitters 11 to 8, transistor 9 will be removed from the saturated state. Therefore, the output current OL does not fluctuate.

そして、上述した二種類の回路動作につき実験データを
とったところ、第4図及び第5図に示す如き特性會得た
。すなわち、本実施例で述べた如く、エミッタE目を接
地してエミッタE1〜E13に人力信号を供給した場合
、トランジスタQ、Iの動作点が第4図に示す如く低下
する。しかし、エミッタE目yk接地し、エミッタgt
t〜E目に人力信号全供給し几場合、トランジスタQ、
tの動作点が第5図に示す如く高くなり、上述の如き欠
陥が現われる。
When experimental data was obtained for the above-mentioned two types of circuit operations, characteristics as shown in FIGS. 4 and 5 were obtained. That is, as described in this embodiment, when emitter E is grounded and human signals are supplied to emitters E1 to E13, the operating points of transistors Q and I are lowered as shown in FIG. However, emitter E eye yk is grounded and emitter gt
If all human input signals are supplied from t to E, transistor Q,
The operating point of t becomes high as shown in FIG. 5, and the above-mentioned defects appear.

以上に述べた理由から、コレクタCに最とも近接シ几ト
ランジスタQ目のエミッタFi t ItJ&地丁れば
、他のエミッタE目〜”Isの何れか′fc接地するエ
リも安定動作金得られることが明らかである。
For the reasons stated above, if the emitter of the transistor Q closest to the collector C is connected to the ground, stable operation can be obtained even if any of the other emitters E to Is are grounded. That is clear.

また、上記トランジスタQ+ kIC化する場合、同一
半導体基板上に多数のものが同時に形成場れる。そして
、エミッタfF2z’e接地すれば安定動作が得られる
ことから、トランジスタQ+ffi第6図に示TV[]
〈同同一面に並べて配置して、接地用回路パターンPを
図示の如<@、線的に設けることができる。仮りに、コ
レクタとベースとが逆方間になるように配置したと丁れ
は、接地用回路パターンPに折線状に設けなければなら
ない。この場合、他の配線パターンと交差する部分が増
加する。しかし、トランジスタQ1を同一方間に並べて
配置することにより、接地用回路パターンPi直線的に
形成することができ、他の回路パターンとの交差を減ら
丁ことかできる。
Furthermore, when the above-mentioned transistor Q+ kIC is fabricated, a large number of transistors are formed simultaneously on the same semiconductor substrate. Since stable operation can be obtained by grounding the emitter fF2z'e, the transistor Q+ffi shown in FIG.
<By arranging them side by side on the same plane, the grounding circuit patterns P can be linearly provided as shown in the figure. If the collector and base are arranged in opposite directions, the grounding circuit pattern P must be provided in the form of a broken line. In this case, the number of intersections with other wiring patterns increases. However, by arranging the transistors Q1 side by side in the same space, the grounding circuit pattern Pi can be formed linearly, and the number of intersections with other circuit patterns can be reduced.

以上に述べた如く、本発明を適用した半導体果柄回路に
XtZば、人力信号をHレベルからLレベルに切換えた
時、出力車流に変動が現われない−ヒに、配線パターン
も簡略化することができる。
As described above, if the semiconductor stalk circuit to which the present invention is applied is used, there will be no fluctuation in the output flow when the human input signal is switched from the H level to the L level.Furthermore, the wiring pattern can be simplified. I can do it.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来公知のショットキーバリアダイオードを有
するマルチエミッタトランジメタの回路図、 第2図は本発明の一実施例奮示すマルチェばツタトラン
ジスタの等価回路図と構造全示す要部の第  3  図 P 第  4 図 ピカ督と 第  5  図 ゴg電圧
FIG. 1 is a circuit diagram of a conventionally known multi-emitter transistor having a Schottky barrier diode, and FIG. 2 is an equivalent circuit diagram of a multi-emitter transistor showing an embodiment of the present invention. Figure P Figure 4 Pika conductor and Figure 5 Gog voltage

Claims (1)

【特許請求の範囲】[Claims] 1、 1?’i]−半4体基板上にマルチエミッタトラ
ンジスタ全回一方回に設け、上記各マルチエミッタトラ
ンジスタの各コレクタに最とも近接したエミツタケ接地
し、他の工εツタに入力16号r供給すること′It竹
徴とする半導体集積回路。
1, 1? 'i] - A multi-emitter transistor is provided on a half-quad board at one time, and the emitter closest to each collector of each of the above-mentioned multi-emitter transistors is grounded, and the input No. 16 r is supplied to the other terminals. 'It is a semiconductor integrated circuit with bamboo characteristics.
JP57113898A 1982-07-02 1982-07-02 Semiconductor integrated circuit Pending JPS595665A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57113898A JPS595665A (en) 1982-07-02 1982-07-02 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57113898A JPS595665A (en) 1982-07-02 1982-07-02 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS595665A true JPS595665A (en) 1984-01-12

Family

ID=14623912

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57113898A Pending JPS595665A (en) 1982-07-02 1982-07-02 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS595665A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5068702A (en) * 1986-03-31 1991-11-26 Exar Corporation Programmable transistor
DE4213606A1 (en) * 1991-04-26 1992-10-29 Toyoda Automatic Loom Works Transistor with current detection property - has main transistor region on substrate also carrying separately arranged measurement regions with common base and collector connections and separate emitter regions
US5200637A (en) * 1988-12-15 1993-04-06 Kabushiki Kaisha Toshiba MOS transistor and differential amplifier circuit with low offset

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5068702A (en) * 1986-03-31 1991-11-26 Exar Corporation Programmable transistor
US5200637A (en) * 1988-12-15 1993-04-06 Kabushiki Kaisha Toshiba MOS transistor and differential amplifier circuit with low offset
DE4213606A1 (en) * 1991-04-26 1992-10-29 Toyoda Automatic Loom Works Transistor with current detection property - has main transistor region on substrate also carrying separately arranged measurement regions with common base and collector connections and separate emitter regions

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