JPS5954269A - Thin film semiconductor device - Google Patents
Thin film semiconductor deviceInfo
- Publication number
- JPS5954269A JPS5954269A JP57165222A JP16522282A JPS5954269A JP S5954269 A JPS5954269 A JP S5954269A JP 57165222 A JP57165222 A JP 57165222A JP 16522282 A JP16522282 A JP 16522282A JP S5954269 A JPS5954269 A JP S5954269A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- semiconductor device
- semiconductor
- conductive film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 28
- 239000010409 thin film Substances 0.000 title description 26
- 239000000758 substrate Substances 0.000 claims description 13
- 239000011521 glass Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 1
- 229920001296 polysiloxane Polymers 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 239000010408 film Substances 0.000 description 28
- 230000003068 static effect Effects 0.000 description 7
- 230000005611 electricity Effects 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
↓発明は、絶縁井智トに形Ｄν（た半涛、体尚膜をｆｆ
ｌいて構成さｉする池暎半導体装１ｒｌ′Ｋ ｆｉｌす
る、従来、ガラス等のイイ・′縁県析十に形成し、た、
アモルファスンリコンヌｄ名結晶ンリ：１ン竺の刊〈型
体薄１換を甲（ハ、マトリックスアト−
スターツエを構成する事は−１−でに知らＪｌている。[Detailed description of the invention] ↓The invention is based on the shape Dν (tahanto, body membrane ff).
Conventionally, semiconductor devices such as glass and the like have been formed in a suitable manner, and
Amorphous Sun Reconne d name crystal non-ri: 1st publication <type body thin 1 conversion part A (ha, matrix at-starts) is known from -1-Jl.
しかるにこの様な半導イイ，氾宿において１Ｆｉ、基板
全体が絶縁層である為に、静ｎｔ気による重荷カマ）
ｌ）ソクスアレー、薄膜１ランジスタ〜１７）半導体薄
膜に蓄積し易く、基板を通じて外部には放電しない為に
、賓易に空気中へ＋７１ ｊＪ’ｉ． ’Ｎ限界工λノ
上に′肛夕「の蓄積する。メジらに、この様？ｊ．湖膜
半嗜体装埴の製造にイオン打込みによる不純物拡散工程
を用いた場合，半導体装１漠内に高濃度のイオンが打込
まね静電気の場合と同様に放電限界ｊＪｌ−に？Ｆ荷が
蓄積される。この結果、半導体薄膜内の１１．荷ｋｊ空
気中へ放電し、この時半導体薄膜がｆＵ傷し、ハＬ′線
ノ切断、素子の破壊が発生する。この様にＰ縁基＆土に
薄膜半導体により素子を構成する」ん′１合、齢Ｎ偲に
極めて弱く、イオン打ち込ノ・技術を月１いる事はでき
１７．い等の不都合が矛・つ介。However, since such a semiconductor is good, it is 1 Fi in a flooded house, and the entire board is an insulating layer, it is a heavy burden due to static air)
l) Sox array, thin film 1 transistor ~ 17) Since it easily accumulates in semiconductor thin films and does not discharge to the outside through the substrate, it easily enters the air +71 jJ'i. Accumulation of ``N'' on the ``N limit process λ''.Is this the case? ?F charges are accumulated at the discharge limit jJl-, as in the case of static electricity.As a result, the 11. charges kj in the semiconductor thin film are discharged into the air, and at this time the semiconductor thin film The fU is damaged, the L' line is cut, and the element is destroyed.In this way, when the element is constructed with a thin film semiconductor on the P edge base and soil, it is extremely weak due to the age of N, and ion bombardment is extremely weak. 17. It is not possible to study technical skills once a month. The inconvenience is the main problem.
木登、明の目的Ｃ１、この様ブエ不都合をｈ ＜ ｌ−
た新規な薄膜半導体装置を提伊することにある。Kinobu, Akira's purpose C1, this kind of inconvenience h < l-
The purpose of this research is to propose a new thin film semiconductor device.
本発明は岸結晶シリコン基板にシリコン酸化膜を介して
薄膜半導体装置を構成した場合、絶糾物基板上へ薄膜半
導体装値を構成したものに比べ、静電気に強く、イオン
打ち込みにおいても半導体薄膜層の損傷が生じにくい事
を巧みに刊用したものである。Ｊユ１下図面により本発
明の詳細な説明する。第１図一本発明による薄膜トラン
ジスターの基本的構法を示すものである。１けガラス等
の絶縁基板でありこの表面全面に導電、′＃膜２を形成
する。一般にカラス基板上に薄膜半導体ｆ構成する装置
は液晶表示パネル等の様に光ｌ・通過し易い事が特徴で
ある為に、第１図内の導電性被膜２も透明ヌは平透明で
ｔｘ （、てはならｌ！い。４゛イ料として、二酸化ス
ズのネー＋ｌ−膜、二酸化スズ含有の酸化インジウム膜
（工、 Ｔ、 Ｏ，膜）等のいわゆる透明導電性膜があ
り、又金属薄膜の場合も膜厚が２００オンゲストｂ−ム
以下てあれげ竿透明とブ、ｒす１８［”目的の導′ｒＭ
悼被膜２として用いる事が司能で力）る。次にこの導電
性被膜２の上に二酸化シリコン、空化シリコン等の絶、
縁＋′Ａ＃′膜３を５０００〜１００００ 、＋ ７
ダストロームの膜ルで形成し、導電性被膜２をおおう。In the present invention, when a thin film semiconductor device is formed on a crystalline silicon substrate via a silicon oxide film, it is more resistant to static electricity than when a thin film semiconductor device is formed on a solid substrate, and even in ion implantation, the semiconductor thin film layer is more resistant to static electricity. This is a clever publication that shows that damage is unlikely to occur. The present invention will be explained in detail with reference to the drawings below. FIG. 1 shows the basic construction method of a thin film transistor according to the present invention. The substrate is an insulating substrate made of glass or the like, and a conductive film 2 is formed on the entire surface thereof. In general, a device constructed of a thin film semiconductor on a glass substrate is characterized by easy passage of light, such as a liquid crystal display panel, so the conductive film 2 in Fig. 1 is also flat and transparent. There are so-called transparent conductive films such as tin dioxide na+l- films and indium oxide films containing tin dioxide. Even in the case of a thin metal film, if the film thickness is less than 200 mm, the rod will be transparent.
It is best to use it as a mourning membrane 2. Next, on this conductive film 2, silicon dioxide, empty silicon, etc.
Edge +'A#' membrane 3 5000~10000, +7
The conductive film 2 is covered with a film of Dastrom.
その徒絶縁性薄膜乙の上へ半漕薄ｌｌωによる７１−リ
ンクヌアレー薄膜トランノスターを作り込む。すなわち
、第１図において、第一層目の多結晶ンリコン４を形成
（−１冬結晶ンリコン４の上へ、ゲート絶縁膜７を形成
し、ゲート絶糾膜７の上へゲート電４ｆｉ８を形成し、
Ｎｉｌ昧トシトランジスター成する。第１図内の５．６
はトランジスターのソース及びドレインである。この様
にガラス等の絶縁基板１上に導電性被膜２人び絶縁膜１
］φ３を介して半導体薄膜層よる素子を構成すれば、邦
結晶シリコン基板十へ二酸化シリコン膜を介して半導体
薄膜による素子を構成した場合と同様に、半導体薄膜に
蓄積ζねた電荷ｄ絶縁被膜ろを渥Ｊ主て、導電性被膜２
に達する。この導電性被膜２一基板１の全面をお卦って
おり半導体薄膜４７！び８」、り面積が大きい為に、導
電性被膜２内の電荷密彦は棒めて小ジ（ｔｒ ｈ、イＩ
Ｙって、半導体薄膜４ヌに８から空気中へ電荷が放電す
る車Ｈ全（ｆｒ くなる。例えば半導体薄膜４及び８の
面積が導電性被膜２の１０分の１であるとすれば本発明
におはる薄膜半導体素子に従来に比べ約１ａ倍静電勿に
強くブｒす、又イオン打し込みにおいでもドーズ閉九し
２て約１０倍の余裕が生−４゛る。A 71-link null array thin film transistor made of half-thin llω is fabricated on top of the insulating thin film B. That is, in FIG. 1, a first layer of polycrystalline silicon 4 is formed (a gate insulating film 7 is formed on the -1 winter crystalline silicon 4, and a gate electrode 4fi8 is formed on the gate insulating film 7). death,
A unique transistor is created. 5.6 in Figure 1
are the source and drain of the transistor. In this way, two conductive films and an insulating film 1 are formed on an insulating substrate 1 such as glass.
] If an element is constructed using a semiconductor thin film layer through φ3, the charge accumulated in the semiconductor thin film ζ and the insulating coating will be reduced in the same manner as when an element is constructed using a semiconductor thin film layer via a silicon dioxide film on a Japanese crystalline silicon substrate. Mainly conductive coating 2
reach. This conductive film 2 covers the entire surface of the substrate 1, and the semiconductor thin film 47! Since the surface area of the conductive film 2 is large, the charge density within the conductive film 2 is quite small (tr h, i I).
Y is the total (fr) of the electric charge discharging into the air from the semiconductor thin films 4 and 8.For example, if the area of the semiconductor thin films 4 and 8 is 1/10 of the conductive film 2, then The thin film semiconductor device according to the invention has an electrostatic charge resistance of about 1a times stronger than that of the conventional device, and also has a dose margin of about 10 times during ion implantation.
第２図は本発明における仙の実施例を示したものであり
、第１図におけると同一部分にＱ」同一・省号を付して
その詳細な説明を省略−する。この実施例における特徴
は絶縁性被膜３入びゲート絶、縁膜７を通してコンタク
トホールを開し１、配、線剖利９により外部と導電性被
膜２が導ガηｎｌ能とｔ【す。コンタクトホールｄ通常
σ’７ｉ）エリチングで行ない、配線部材９は、辻漕体
薄膜の４でも８でもどちらでもμい。第２図の様な構成
にする事により配ａ９をさらに外部へアースする事が可
能であり静電気及びイオン打ち込入等により半導体薄膜
４及び８に蓄積する電荷を導電性簿膜２を通して積権的
に外部へ放電する事となり、静電気に対しても又イメン
杓ち込みにし′？イ、智らに破壊ＩＴＩＩ丘が向上する
効果をもたらす。FIG. 2 shows an embodiment of the present invention, and the same parts as in FIG. The feature of this embodiment is that the contact hole 1 is opened through the insulating film 3, the gate insulation, and the insulation film 7, and the conductive film 2 is connected to the outside by the conductive film 2 due to the wiring and wiring geometry 9. The contact hole d is usually σ'7i) made by etching, and the wiring member 9 has a diameter of either 4 or 8 made of a cross-body thin film. By configuring as shown in Fig. 2, it is possible to further ground the distribution a9 to the outside, and the electric charge accumulated in the semiconductor thin films 4 and 8 due to static electricity and ion implantation can be transferred through the conductive film 2. Therefore, static electricity will be discharged to the outside, and static electricity will also be affected. B. It gives Tomo et al. the effect of improving the destroyed ITII hill.
旬十オ・発Ｉ叫によれば半導体薄膜のＦ’ ｆｌｌ＋に
顔・ｔ＃膜折−介して導電被膜を設ける事により、薄膜
半導体素子の静電気耐弾が増（、イオン↑］ち泌みによ
る１ｆ１傷も防１１する事が可能となる。According to Junjuo's report, by providing a conductive film on the F' fll+ of the semiconductor thin film through the face/t# film fold, the electrostatic bullet resistance of the thin film semiconductor element can be increased (, ion ↑). It is also possible to prevent 1f1 damage due to
第１図は本発明にｂ ｌ−する笑施例を示した断面図で
あり、第２図は本発明におし）る仙σ）′＃施例を示し
ｐ断面図である。
１・・・・・・ガラス基（Ｎ
２・・・・透明導筒（／１被膜
３・・・・・絶縁性被膜
４．８・・・・・・半導体薄膜
７・・・・・・ゲート絶縁膜
？ ・・・へｅ線部椙
り上FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is a sectional view of an embodiment of the present invention. 1...Glass base (N2...Transparent conductor (/1) Coating 3...Insulating coating 4.8...Semiconductor thin film 7... Gate insulating film? ... above the e-line part
Claims (2)
リコン、多結晶シリコン等の半導体物質により素子を形
成して成る半導体装置において、前記絶縁基板上へまず
、ネサ膜、］’ ｉ’ ０膜等の透明導電性被膜か又は
２００オンゲスト「「−ム旬下の膜１坪の半透明金属層
膜を形成し、該透明導電、膜又Ｖま、半透明金属層膜の
」ニへ二酸化シリコンヌは窒化シリコン等の絶縁層を形
成し、該絶縁層の上べ前記半導体物質による素子を形成
する事を特徴とする半導体装置。(1) In a semiconductor device in which an element is formed using a semiconductor material such as amorphous silicon or polycrystalline silicon on a substrate such as a glass substrate, a nesa film or a ]'i' 0 film is first applied to the insulating substrate. Form a transparent conductive film such as 200 onguest "-1 tsubo of a semi-transparent metal layer film, and add 200% of the transparent conductive film or the semi-transparent metal layer film" to dioxide. A semiconductor device characterized in that silicone is formed with an insulating layer such as silicon nitride, and an element made of the semiconductor material is formed on top of the insulating layer.
記絶縁基板外へ導通をとる構造を有している事を特徴と
する特許語意の範囲第１項記載の半導体装置。(2) The semiconductor device according to item 1 of the patent scope, wherein the transparent conductive film 5/ is characterized in that the translucent metal layer has a structure that provides conduction to the outside of the insulating substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57165222A JPS5954269A (en) | 1982-09-22 | 1982-09-22 | Thin film semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57165222A JPS5954269A (en) | 1982-09-22 | 1982-09-22 | Thin film semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5954269A true JPS5954269A (en) | 1984-03-29 |
Family
ID=15808167
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57165222A Pending JPS5954269A (en) | 1982-09-22 | 1982-09-22 | Thin film semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5954269A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62171161A (en) * | 1986-01-23 | 1987-07-28 | Nec Corp | thin film semiconductor device |
| EP0601652A2 (en) * | 1992-12-11 | 1994-06-15 | Philips Electronics Uk Limited | Electronic device manufacture using ion implantation |
| WO2002039504A1 (en) * | 2000-11-10 | 2002-05-16 | Citizen Watch Co., Ltd. | Solar cell module and portable electronic apparatus with it |
| US7491969B2 (en) | 2005-09-15 | 2009-02-17 | Au Optronics Corp. | Organic light emitting diode display |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57104261A (en) * | 1980-11-03 | 1982-06-29 | Xerox Corp | Film transistor array and method of producing same |
| JPS57104260A (en) * | 1980-11-03 | 1982-06-29 | Xerox Corp | Thin film transistor and method of producing same array |
-
1982
- 1982-09-22 JP JP57165222A patent/JPS5954269A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57104261A (en) * | 1980-11-03 | 1982-06-29 | Xerox Corp | Film transistor array and method of producing same |
| JPS57104260A (en) * | 1980-11-03 | 1982-06-29 | Xerox Corp | Thin film transistor and method of producing same array |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62171161A (en) * | 1986-01-23 | 1987-07-28 | Nec Corp | thin film semiconductor device |
| EP0601652A2 (en) * | 1992-12-11 | 1994-06-15 | Philips Electronics Uk Limited | Electronic device manufacture using ion implantation |
| EP0601652A3 (en) * | 1992-12-11 | 1998-02-25 | Philips Electronics Uk Limited | Electronic device manufacture using ion implantation |
| WO2002039504A1 (en) * | 2000-11-10 | 2002-05-16 | Citizen Watch Co., Ltd. | Solar cell module and portable electronic apparatus with it |
| US7057102B2 (en) | 2000-11-10 | 2006-06-06 | Citizen Watch Co., Ltd. | Solar cell module and portable electronic apparatus with it |
| US7491969B2 (en) | 2005-09-15 | 2009-02-17 | Au Optronics Corp. | Organic light emitting diode display |
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