JPS5952584B2 - Digital modulated wave transmission method - Google Patents
Digital modulated wave transmission methodInfo
- Publication number
- JPS5952584B2 JPS5952584B2 JP17308479A JP17308479A JPS5952584B2 JP S5952584 B2 JPS5952584 B2 JP S5952584B2 JP 17308479 A JP17308479 A JP 17308479A JP 17308479 A JP17308479 A JP 17308479A JP S5952584 B2 JPS5952584 B2 JP S5952584B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- level
- circuit
- gain
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G7/00—Volume compression or expansion in amplifiers
- H03G7/007—Volume compression or expansion in amplifiers of digital or coded signals
Landscapes
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
- Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
Description
【発明の詳細な説明】
本発明はディジタル変調波伝送方式に係り、少フない伝
送ビットでその制限されたビット数を越える品質のディ
ジタル変調波を伝送しうる方式を提供することを目的と
する。[Detailed Description of the Invention] The present invention relates to a digital modulated wave transmission system, and an object thereof is to provide a system that can transmit a digital modulated wave of quality exceeding the limited number of bits with a small number of transmission bits. .
第1図は従来のディジタル変調波伝送方式の一例のブロ
ック系統図を示す。FIG. 1 shows a block system diagram of an example of a conventional digital modulated wave transmission system.
同図中、入力端子1門に入来したアナログ信号は低域フ
ィルタ2に供給され、ここで不要な高域成分が除去され
た後サンプリングホールド回路3に供給され、ここでサ
ンプリングホールドされる。サンプリングホールド回路
3より取り出された時間的に離散化された標1本化信号
は、後述の可変利得器7を通してAD変換器8に印加さ
れる一方、絶対値回路4に供給され、ここで絶対値をと
られる。この絶対値回路4の出力信号は、電圧比較器6
に供給され、ここで基準電圧設定器5よりの基準電圧と
比較され、基準電圧を越えた時可変利得器7の利得を可
変せしめる。第2図は上記の利得制御が行なわれる可変
利得器7の入力電圧対出力電圧特性を示す。In the figure, an analog signal entering one input terminal is supplied to a low-pass filter 2, where unnecessary high-frequency components are removed, and then supplied to a sampling and holding circuit 3, where it is sampled and held. The temporally discretized sampled signal extracted from the sampling and hold circuit 3 is applied to an AD converter 8 through a variable gain device 7, which will be described later, and is also supplied to an absolute value circuit 4, where the absolute value value is taken. The output signal of this absolute value circuit 4 is sent to a voltage comparator 6
Here, it is compared with the reference voltage from the reference voltage setter 5, and when it exceeds the reference voltage, the gain of the variable gain unit 7 is varied. FIG. 2 shows the input voltage versus output voltage characteristics of the variable gain device 7 in which the above gain control is performed.
同図よりもわかるように、入力電圧の絶対値が大になり
、AD変換器8によつて伝送しうる最大又は最小の入力
電圧となつたときは、上記の電圧比較器6よりの利得制
御信号によつて利得が可変せしめられる結果、出力電圧
の絶対値が減衰せしめられる。この結果、可変利得器7
の出力電圧は常にAD変換器8のビット数によつて定ま
る所定電圧範囲(第2図に±1で示す)内とされ、第3
図に示す如き波形となる。上記可変利得器7の出力電圧
はAD変換器8に供給され、ここでアナログーデイジタ
ル変換されて(具体的には量子化、符号化されて)パル
ス符号変調(PCM)信号等のデイジタル変調波とされ
る。As can be seen from the figure, when the absolute value of the input voltage becomes large and reaches the maximum or minimum input voltage that can be transmitted by the AD converter 8, the gain control from the voltage comparator 6 is performed. As a result of varying the gain depending on the signal, the absolute value of the output voltage is attenuated. As a result, variable gain device 7
The output voltage of the third
The waveform will be as shown in the figure. The output voltage of the variable gain device 7 is supplied to the AD converter 8, where it is analog-to-digital converted (specifically, quantized and encoded) into a digital modulated wave such as a pulse code modulation (PCM) signal. It is said that
このデイジタル変調波は所定の伝送路を経てDA変換器
9に供給され、ここでデイジタルアナログ変換された後
可変利得器10により送信系でルベル減衰又はレベル増
強された分が元に戻され、更に低域フイルタ11により
元のアナログ信号に復元されて出力端子12より出力さ
れる。しかるに、上記の従来のデイジタル変調波伝送方
式は、送信側の可変利得器7で利得制御した分と逆方向
で、かつ、同じ量だけ受信側の可変利得器10で制御さ
せるための、可変利得器制御用信号も伝送信号として同
時に伝送しなければならなかつたため、伝送ビツト数の
削減化という要求に制限を与えていた。本発明は上記欠
点を除去したものであり、以下図面と共にその一実施例
について説明する。This digitally modulated wave is supplied to the DA converter 9 via a predetermined transmission path, where it is digital-to-analog converted, and then the level attenuated or level-enhanced in the transmission system is restored by the variable gainer 10. The signal is restored to the original analog signal by the low-pass filter 11 and output from the output terminal 12. However, in the conventional digital modulated wave transmission method described above, the variable gain is controlled by the variable gain unit 10 on the receiving side in the opposite direction and by the same amount as the gain controlled by the variable gain unit 7 on the transmitting side. Since device control signals also had to be transmitted at the same time as transmission signals, the demand for reducing the number of transmission bits was limited. The present invention eliminates the above-mentioned drawbacks, and an embodiment thereof will be described below with reference to the drawings.
第4図は本発明になるデイジタル変調波伝送方式の一実
施例のプロツク系統図を示す。同図中、第1図と同一部
分には同一番号を付し、その説明を省略する。第4図に
おいて、サンプリングホールド回路3より取り出された
標本化信号は、破線13で示す信号予測回路に供給され
る一方、利得制御器24に供給される。信号予測回路1
3に供給されたサンプリングホールド回路3の出力信号
は、まず絶対値回路14に供給され、ここで絶対値がと
られて遅延器15及び加算器17に夫々供給される。遅
延器15はサンプリングホールド回路3の一サンプリン
ダ周期に等しい時間入力信号を遅延してインバータ16
を通してその出力遅延信号を加算器17に供給する。加
算器17の出力信号は利得制御器18で適当な重み付け
のための利得制御がなされた後、加算器19に供給され
、ここで絶対値回路14の出力信号と加算される。従つ
て、加算器19は絶対値回路14よりの信号と、これよ
リーサンプリング周期前の利得制御器18の出力信号(
微係数検出信号)とを加算することとなり、これにより
予測信号を出力する。すなわち、絶対値回路14の出力
標本化信号のアナログ換算レベルの一例を第5図に実線
の矢印で示すものとすると、ある時刻t1におけるアナ
ログ換算レベルとt1によリーサンプリング周期経過′
した時刻T2におけるアナログ換算レベルとの差分dを
示す標本化信号(差分信号)が加算器17より時刻T2
で出力され、更に利得制御器18でαなる重み付け係数
と乗算されて加算器19に供給されるので、加算器19
の出力信号のアナログ換算レベルは、時刻T2における
絶対値回路14の出力アナログ換算レベルと上記αdな
る差分信号のアナログ換算レベルとの和となり、第5図
に時刻T3の破線の矢印1で示す如くになる。FIG. 4 shows a block system diagram of an embodiment of the digital modulated wave transmission system according to the present invention. In the figure, the same parts as in FIG. 1 are given the same numbers, and their explanations will be omitted. In FIG. 4, the sampled signal taken out from the sampling and holding circuit 3 is supplied to a signal prediction circuit indicated by a broken line 13, and is also supplied to a gain controller 24. Signal prediction circuit 1
The output signal of the sampling hold circuit 3 is first supplied to an absolute value circuit 14, where the absolute value is taken and supplied to a delay device 15 and an adder 17, respectively. The delay device 15 delays the input signal for a time equal to one sampler cycle of the sampling and holding circuit 3, and outputs the signal to the inverter 16.
The output delayed signal is supplied to the adder 17 through. The output signal of the adder 17 is subjected to gain control for appropriate weighting by a gain controller 18, and then supplied to an adder 19, where it is added to the output signal of the absolute value circuit 14. Therefore, the adder 19 combines the signal from the absolute value circuit 14 and the output signal (
(differential coefficient detection signal), thereby outputting a predicted signal. That is, if an example of the analog conversion level of the output sampling signal of the absolute value circuit 14 is shown by the solid arrow in FIG. 5, the analog conversion level at a certain time t1 and the elapsed sampling period '
The sampled signal (difference signal) indicating the difference d from the analog conversion level at time T2 is output from the adder 17 to time T2.
is output, further multiplied by a weighting coefficient α in the gain controller 18, and supplied to the adder 19, so the adder 19
The analog conversion level of the output signal is the sum of the output analog conversion level of the absolute value circuit 14 at time T2 and the analog conversion level of the difference signal αd, as shown by the broken line arrow 1 at time T3 in FIG. become.
この破線の矢印1で示す予測信号は時刻T3に絶対値回
路14より得られる出力のアナログ換算レベルを予測す
る信号として、時刻T2に得られる。なお、実線の矢印
11は時刻T2よリーサンプリング周期後の時刻T3に
おける実際の絶対値回路14の出力アナログ換算レベル
を示し、予測信号に近似したレベルである。本発明はこ
の予測信号に基づいてAD変換器8の入力信号レベルを
制御して伝送し、これを受信側で送信側とは逆のレベル
制御を行なうことにより、一定のビツト数のデイジタル
変調波の伝送を、制御信号用ビツトを不要として行なう
ようにしたものである。The predicted signal indicated by the broken arrow 1 is obtained at time T2 as a signal that predicts the analog conversion level of the output obtained from the absolute value circuit 14 at time T3. Note that the solid arrow 11 indicates the actual analog conversion level of the output of the absolute value circuit 14 at time T3, which is a sampling cycle after time T2, and is a level that approximates the predicted signal. The present invention controls and transmits the input signal level of the AD converter 8 based on this predicted signal, and performs level control on the receiving side that is opposite to that on the transmitting side, thereby generating a digital modulated wave with a fixed number of bits. The transmission is performed without the need for control signal bits.
加算器19より取り出された予測信号は比較器20,2
1に供給され、上限レベル設定器22、下限レベル設定
器23の出力信号レベルとレベル比較される。The predicted signal taken out from the adder 19 is sent to comparators 20 and 2.
1, and the level is compared with the output signal level of the upper limit level setter 22 and the lower limit level setter 23.
上限レベル設定器22の設定上限レベルと下限レベル設
定器23の設定下限レベルとの差のレベル範囲が、少な
いビツト数のAD変換器8にて伝送しうる一定のレベル
範囲を示し、予測信号レベルが設定上限レベルよりも大
レベルとなつたときはこのレベル範囲全体が上方へシフ
トされ、他方、予測信号レベルが設定下限レベルよりも
小レベルとなつたときはこのレベル範囲全体が下方へシ
フトされる。例えば、第6図に示す如く設定上限レベル
が111.設定下限レベルがIVで示す状態において、
時刻T2で得られた時刻T3の破線の矢印で示す絶対値
回路14の出力アナログ換算レベルの予測値が、設定上
限レベル111を越えたときは、比較器20より上限レ
ベル設定器22の設定上限レベルが111″で示す如く
その予測値よりも大とするための信号が出力されると同
時に、下限レベル設定器23の設定下限レベルもIV″
で示す如くに同じ量だけ大とされる。The level range of the difference between the upper limit level set by the upper limit level setter 22 and the lower limit level set by the lower limit level setter 23 indicates a certain level range that can be transmitted by the AD converter 8 with a small number of bits, and the predicted signal level When the predicted signal level becomes higher than the set upper limit level, this entire level range is shifted upward, and on the other hand, when the predicted signal level becomes lower than the set lower limit level, this entire level range is shifted downward. Ru. For example, as shown in FIG. 6, the set upper limit level is 111. In the state where the setting lower limit level is indicated by IV,
When the predicted value of the output analog conversion level of the absolute value circuit 14 indicated by the dashed arrow at time T3 obtained at time T2 exceeds the set upper limit level 111, the comparator 20 determines the set upper limit of the upper limit level setter 22. At the same time, a signal is output to make the level higher than the predicted value as shown by 111'', and at the same time, the lower limit level set by the lower limit level setter 23 is also set to IV''.
As shown in , it is increased by the same amount.
またこれと同時に、比較器20は利得制御器24へ利得
を小とするための制御信号を出力し、利得制御器24よ
りAD変換器8へ時刻T3に供給される信号レベルを所
定レベル減衰させる。一方、時刻Tn+1で得られた時
刻Tn+2の予測信号レベルが第6図に破線の矢印で示
す如く今までの設定下限レベルよりも小となつたときは
、比較器21より下限レベル設定器23の設定下限レベ
ルがI″″で示す如く上記Tn+2の予測信号レベルよ
りも低くするための信号が出力されると同時に、上限レ
ベル設定器22の設定上限レベルもII『″で示す如く
同じ量だけ小とするための信号が出力される。At the same time, the comparator 20 outputs a control signal to the gain controller 24 to reduce the gain, and attenuates the signal level supplied from the gain controller 24 to the AD converter 8 at time T3 by a predetermined level. . On the other hand, when the predicted signal level at time Tn+2 obtained at time Tn+1 becomes smaller than the previously set lower limit level as shown by the broken line arrow in FIG. At the same time that a signal is output to make the set lower limit level lower than the predicted signal level of Tn+2, as shown by I'''', the set upper limit level of the upper limit level setter 22 is also lowered by the same amount, as shown by II''. A signal is output for this purpose.
またこれと同時に、比較器21は利得制御器24へ利得
を大とするための制御信号を出力し、利得制御器24よ
りAD変換器8へ時刻Tn+2に供給される信号レベル
を所定レベル増強させる。このようにして、利得制御器
24より出力されてAD変換器8へ供給される信号(標
本化信号)のアナログ換算レベルは、AD変換器8によ
り高品質で伝送しうるレベル範囲内とされ、常にレベル
変化の大きい方に追随制御される。At the same time, the comparator 21 outputs a control signal to increase the gain to the gain controller 24, and increases the signal level supplied from the gain controller 24 to the AD converter 8 at time Tn+2 by a predetermined level. . In this way, the analog conversion level of the signal (sampled signal) output from the gain controller 24 and supplied to the AD converter 8 is set within a level range that can be transmitted with high quality by the AD converter 8, Control is always performed to follow the one with the largest level change.
従つて、レベル変化の大きい信号入力のときは量子化の
最低レベルが上がり、逆にレベル変化の小さい場合は量
子化の最低レベルが下がり、より細かい量子化が行なわ
れる。なお、第7図は利得制御器24のアナログ換算し
た入出力特性を示し、実線Vはある時刻における入出力
特性、一点鎖線VIは他の時刻における入出力特性を示
し、ダイナミツクレンジPは一定である。上記の如くに
して得られた利得制御器24の出力信号は、AD変換器
8によりデイジタル変調波(例えばPCM信号)とされ
て伝送路を経て伝送された後、第4図示の受信側のDA
変換器9に供給され、ここでデイジタルーアナログ変換
された後サンプリングホールド回路25及び利得制御器
27に夫々供給される。Therefore, when a signal input with a large level change is input, the lowest level of quantization is increased, and conversely, when a level change is small, the lowest level of quantization is lowered, and finer quantization is performed. Note that FIG. 7 shows the analog converted input/output characteristics of the gain controller 24, where the solid line V shows the input/output characteristics at a certain time, the dashed line VI shows the input/output characteristics at other times, and the dynamic range P is constant. It is. The output signal of the gain controller 24 obtained as described above is converted into a digitally modulated wave (for example, a PCM signal) by the AD converter 8, and is transmitted via a transmission path, and is then transmitted to the receiving side DA shown in FIG.
The signal is supplied to a converter 9, where it is subjected to digital-to-analog conversion, and then supplied to a sampling hold circuit 25 and a gain controller 27, respectively.
サンプリングホールド回路25の出力信号は、信号予測
回路26に供給される。信号予測回路26は信号予測回
路13と同様の回路構成とされているが、予測信号レベ
ルが上限設定レベルよりも大となつたときは上限及び下
限設定レベルを所定量大とすると同時に、利得制御器2
7の利得を所定の利得に増加させる制御信号を出力し、
他方、予測信号レベルが下限設定レベルよりも小となつ
たときは上限及び下限設定レベルを夫々小とすると同時
に、利得制御器27の利得を所定の利得に減少させる制
御信号を出力する点が、信号予測回路13と異なる。The output signal of the sampling and holding circuit 25 is supplied to a signal prediction circuit 26. The signal prediction circuit 26 has the same circuit configuration as the signal prediction circuit 13, but when the predicted signal level becomes higher than the upper limit setting level, the upper limit and lower limit setting levels are increased by a predetermined amount, and at the same time, gain control is performed. Vessel 2
output a control signal to increase the gain of 7 to a predetermined gain;
On the other hand, when the predicted signal level becomes smaller than the lower limit setting level, the upper limit setting level and the lower limit setting level are respectively reduced, and at the same time, a control signal is outputted to reduce the gain of the gain controller 27 to a predetermined gain. This is different from the signal prediction circuit 13.
このようにして得られた利得制御器27の出力信号は低
域フイルタ11を通されることにより、原アナログ信号
に復元されて出力端子12より出力される。The output signal of the gain controller 27 obtained in this manner is passed through the low-pass filter 11, restored to the original analog signal, and outputted from the output terminal 12.
本実施例によれば、信号予測回路13,26を設け、標
本化信号より得た予測信号レベルが上限又は下限設定レ
ベルを越えたか否かによつて利得制御器24,27の制
御信号を得るようにしているから、特別に利得制御用信
号を伝送する必要は全く無く、従つて従来より少ないビ
ツト数でデイジタル変調波を伝送でき、また入力アナロ
グ信号レベルが小なるときは量子化の最低レベルが下が
り、より細かい量子化が行なえ、量子化ノイズが低減す
る。According to this embodiment, the signal prediction circuits 13 and 26 are provided, and control signals for the gain controllers 24 and 27 are obtained depending on whether the predicted signal level obtained from the sampled signal exceeds the upper limit or lower limit set level. Therefore, there is no need to transmit a special gain control signal, and the digital modulated wave can be transmitted with a smaller number of bits than before, and when the input analog signal level is small, the lowest level of quantization can be used. is lowered, finer quantization can be performed, and quantization noise is reduced.
なお、上記の実施例では予測信号を隣接する標本化信号
より得ているが、ニサンプリング周期と一サンプリング
周期夫々前の標本化信号の平均値と現時刻の標本化信号
とを夫々用いて得るようにしてもよい。In the above embodiment, the predicted signal is obtained from the adjacent sampled signals, but it is obtained by using the average value of the sampled signal two sampling periods and one sampling period ago, respectively, and the sampled signal at the current time. You can do it like this.
上述の如く、本発明になるデイジタル変調波伝送方式は
、サンプルホールド回路の出力信号の絶対値出力とその
差分信号とより予測信号を得、制御回路により予測信号
のアナログ換算レベルが予め設定した上限レベルと下限
レベルとの間の設定ノレベル範囲を越えたときのみ、上
記サンプルホールド回路の出力信号が供給される第1の
利得制御器の利得を、上記上限レベルより大のときは小
に、また上記下限レベルより小のときは大に制御すると
共に、上記上限レベルと下限レベルとを上記予測信号の
アナログ換算レベルが上記設定レベル範囲内のレベルと
なるように変更し、第1の利得制御器の出力信号をAD
変換器によりデイジタル変調波として伝送し、伝送され
たデイジタル変調波がDA変換器を通して供給される第
2の利得j制御器の利得を上記制御回路とは逆の動作を
行なう信号予測回路によつて制御し、上記第2の利得制
御器の出力信号を原アナログ信号に復調するようにした
ため、AD変換器やDA変換器の変換精度が低くてもそ
の入力信号レベルが制御されるので、その性能以上の高
品質の信号伝送ができ、また受信側へ利得制御用信号を
伝送する必要が全くないので、従来よりも少ないビツト
数でデイジタル変調波を伝送でき、また入力アナログ信
号レベルが小なるときは量子化の最低レベルを下げてよ
り細かな量子化を行なうので量子化ノイズを低減でき、
以上より少ない限られたビツト数でデイジタル変調波の
伝送を高品質で行なえる等の特長を有するものである。As described above, the digital modulated wave transmission method according to the present invention obtains a predicted signal from the absolute value output of the output signal of the sample-and-hold circuit and its difference signal, and controls the analog conversion level of the predicted signal to a preset upper limit using the control circuit. Only when the set level range between the level and the lower limit level is exceeded, the gain of the first gain controller to which the output signal of the sample and hold circuit is supplied is set to be small when the output signal is higher than the upper limit level, and When it is smaller than the lower limit level, it is controlled to be higher, and the upper limit level and lower limit level are changed so that the analog equivalent level of the predicted signal is within the set level range, and the first gain controller The output signal of
The gain of the second gain j controller is transmitted as a digital modulated wave by the converter, and the transmitted digital modulated wave is supplied through the DA converter by a signal prediction circuit that performs an operation opposite to that of the control circuit. Since the output signal of the second gain controller is demodulated into the original analog signal, the input signal level can be controlled even if the conversion accuracy of the AD converter or DA converter is low. In addition, there is no need to transmit a gain control signal to the receiving side, so digitally modulated waves can be transmitted with fewer bits than before, and when the input analog signal level is low. lowers the minimum level of quantization and performs finer quantization, which reduces quantization noise.
It has the advantage of being able to transmit digitally modulated waves with high quality using a limited number of bits, which is smaller than the above.
第1図は従来方式の一例を示すプロツク系統図、第2図
は送信側の可変利得器の入出力特性を示す図、第3図は
送信側の可変利得器の出力信号波形の一例を示す図、第
4図は本発明方式の一実施例を示すプロツク系統図、第
5図は本発明方式の一要部の動作原理を説明するための
アナログ換算レベルを示す図、第6図は本発明方式の他
の要部の動作を説明するための図、第7図は本発明方式
の送信側の利得制御器の入出力特性の一例を示す図であ
る。
1・・・・・・アナログ信号入力端子、3,25・・・
・・・サンプリングホールド回路、8・・・・・・AD
変換器、9・・・・・・DA変換器、12・・・・・・
アナログ信号出力端子、13,26・・・・・・信号予
測回路、14・・・・・・絶対値回路、15・・・・・
・遅延器、17,19・・・・・・加算器、20,21
・・・・・・比較器、22・・・・・・上限レベル設定
器、23・・・・・・下限レベル設定器、24,27・
・・・・・利得制御器。Figure 1 is a block system diagram showing an example of the conventional method, Figure 2 is a diagram showing the input/output characteristics of the variable gain unit on the transmitting side, and Figure 3 is an example of the output signal waveform of the variable gain unit on the transmitting side. 4 is a block system diagram showing an embodiment of the method of the present invention, FIG. 5 is a diagram showing an analog conversion level for explaining the operating principle of the main part of the method of the present invention, and FIG. 6 is a diagram of the present invention. FIG. 7, which is a diagram for explaining the operation of other main parts of the inventive system, is a diagram showing an example of the input/output characteristics of the gain controller on the transmitting side of the inventive system. 1...Analog signal input terminal, 3, 25...
...Sampling hold circuit, 8...AD
Converter, 9...DA converter, 12...
Analog signal output terminal, 13, 26...signal prediction circuit, 14...absolute value circuit, 15...
・Delay device, 17, 19... Adder, 20, 21
... Comparator, 22 ... Upper limit level setter, 23 ... Lower limit level setter, 24, 27.
...Gain controller.
Claims (1)
ルド回路と、該サンプルホールド回路の出力信号レベル
を可変出力する第1の利得制御器と、該サンプルホール
ド回路の出力信号の絶対値出力を得る絶対値回路と、該
絶対値回路の絶対値出力信号が供給されその少なくとも
一サンプリング周期以上前の信号と現時刻の信号との差
分に相当する差分信号を出力する差分回路と、該絶対値
回路と該差分回路の両出力信号を夫々加算して予測信号
を出力する加算回路と、該予測信号のアナログ換算レベ
ルが予め設定した上限レベルと下限レベルとの間の設定
レベル範囲を越えたときのみ該第1の利得制御器の利得
を上記上限レベルより大のときは小に、また上記下限レ
ベルより小のときは大に制御すると共に、上記上限レベ
ルと下限レベルとを上記予測信号のアナログ換算レベル
が上記設定レベル範囲内のレベルとなるように変更する
制御回路と、該第1の利得制御器の出力信号をディジタ
ル変調波とするAD変換器と、伝送路を経た該ディジタ
ル変調波がDA変換器を通して供給される第2の利得制
御器と、該DA変換器の出力が供給されこれより送信側
の該絶対値回路、差分回路、加算回路及び制御回路とよ
りなる回路構成と同様の回路構成により上記第1の利得
制御器の制御動作とは逆の利得制御動作を該第2の利得
制御器に対して行なう信号予測回路と、該第2の利得制
御器の出力信号を原アナログ信号に復調する回路とより
構成したことを特徴とするディジタル変調波伝送方式。1. A sample and hold circuit that samples and holds an analog signal, a first gain controller that outputs a variable output signal level of the sample and hold circuit, and an absolute value circuit that obtains an absolute value output of the output signal of the sample and hold circuit. a difference circuit which is supplied with the absolute value output signal of the absolute value circuit and outputs a difference signal corresponding to the difference between the signal at least one sampling period or more earlier and the signal at the current time; and the absolute value circuit and the difference circuit. an adder circuit that adds both output signals to output a predicted signal; and the first gain is applied only when the analog conversion level of the predicted signal exceeds a preset level range between a preset upper limit level and a lower limit level. The gain of the controller is controlled to be small when the gain is larger than the above upper limit level, and large when it is smaller than the above lower limit level, and the above upper limit level and lower limit level are set so that the analog conversion level of the above predicted signal is the above set level. a control circuit that changes the level so that the level is within a range; an AD converter that converts the output signal of the first gain controller into a digital modulated wave; and the digital modulated wave that has passed through the transmission line is supplied through the DA converter. A circuit configuration similar to the circuit configuration consisting of the second gain controller, the absolute value circuit, the difference circuit, the adder circuit, and the control circuit on the transmitting side to which the output of the DA converter is supplied is used. a signal prediction circuit that performs a gain control operation on the second gain controller that is opposite to the control operation of the gain controller; and a circuit that demodulates the output signal of the second gain controller into an original analog signal. A digital modulated wave transmission system characterized by having a structure of:
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17308479A JPS5952584B2 (en) | 1979-12-27 | 1979-12-27 | Digital modulated wave transmission method |
NLAANVRAGE8006810,A NL190093C (en) | 1979-12-17 | 1980-12-16 | COMPRESSING AND EXPANDING SYSTEM. |
DE3047447A DE3047447C2 (en) | 1979-12-17 | 1980-12-17 | Digital amplifier for expanding or narrowing the dynamic range of a digital input signal sent to the amplifier as required |
GB8040416A GB2070361B (en) | 1979-12-17 | 1980-12-17 | Gain control |
US06/217,949 US4355304A (en) | 1979-12-17 | 1980-12-18 | Digital compandor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17308479A JPS5952584B2 (en) | 1979-12-27 | 1979-12-27 | Digital modulated wave transmission method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5694855A JPS5694855A (en) | 1981-07-31 |
JPS5952584B2 true JPS5952584B2 (en) | 1984-12-20 |
Family
ID=15953904
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17308479A Expired JPS5952584B2 (en) | 1979-12-17 | 1979-12-27 | Digital modulated wave transmission method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5952584B2 (en) |
-
1979
- 1979-12-27 JP JP17308479A patent/JPS5952584B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5694855A (en) | 1981-07-31 |
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