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JPS5951601A - microwave integrated circuit - Google Patents

microwave integrated circuit

Info

Publication number
JPS5951601A
JPS5951601A JP13757182A JP13757182A JPS5951601A JP S5951601 A JPS5951601 A JP S5951601A JP 13757182 A JP13757182 A JP 13757182A JP 13757182 A JP13757182 A JP 13757182A JP S5951601 A JPS5951601 A JP S5951601A
Authority
JP
Japan
Prior art keywords
bias circuit
circuit
bias
circulator
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13757182A
Other languages
Japanese (ja)
Inventor
Masayuki Ishizaki
石崎 正之
Hideo Sugawara
菅原 秀夫
Shinichi Moriyama
伸一 森山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13757182A priority Critical patent/JPS5951601A/en
Publication of JPS5951601A publication Critical patent/JPS5951601A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P1/00Auxiliary devices
    • H01P1/20Frequency-selective devices, e.g. filters
    • H01P1/201Filters for transverse electromagnetic waves
    • H01P1/203Strip line filters

Landscapes

  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Waveguide Connection Structure (AREA)
  • Microwave Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (a)  発明の技術分野 本発明は発振又は増lJ用半導体素子と種々の回路全集
積したマイクロ波0積回路よシなる発振器又は増巾器に
係りバイアス回路の該半導体素子への影咎ヲなくするマ
イクロ波集積回路に関する。
Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to an oscillator or amplifier such as a microwave zero-product circuit in which a semiconductor element for oscillation or amplification and various circuits are fully integrated. This invention relates to a microwave integrated circuit that eliminates the influence on semiconductor devices.

(bl  従来技術と問題点 第1図は従来例の発振器の平面図、第2図は従来例のj
口中器の平面図、第3図は第1図の直流カント部の外側
を終端し、ガンΦインパットダイオード2の代わシに同
軸線路を用いガン・インバットダイオード2の位置よシ
見たインピーダンスの特性図で、実線はバイアス回路5
が無い場合、点線はバイアス回路5がある場合金示す。
(bl Conventional technology and problems Figure 1 is a plan view of a conventional oscillator, and Figure 2 is a diagram of a conventional oscillator.
A plan view of the mouth organ, Figure 3 shows the impedance as seen from the position of the gun-input diode 2, using a coaxial line in place of the gun Φ impact diode 2, terminating the outside of the DC cant part in Figure 1. In the characteristic diagram, the solid line is bias circuit 5
If there is no bias circuit 5, the dotted line indicates if there is a bias circuit 5.

図中1は共振器、2はガン・インバットダイオード、3
,17.18は直流カット用結合線路、4はインピーダ
ンス変成器、5.11.12はバイアス回路、6.1’
3.14はサーキュレータ、7.15゜16はダミーロ
ード、8は電界効果トランジスタ。
In the figure, 1 is a resonator, 2 is a gun inbat diode, and 3
, 17.18 is a coupled line for DC cut, 4 is an impedance transformer, 5.11.12 is a bias circuit, 6.1'
3.14 is a circulator, 7.15°16 is a dummy load, and 8 is a field effect transistor.

9は入力整合回路、10は出力整合回路を示す。9 indicates an input matching circuit, and 10 indicates an output matching circuit.

マイクロ波からミリ波に及ぶ範囲でマイクロ波集積回路
を利用した発振器及び増巾器が作られており、一般的に
はマイクロ波帯ではバイポーラトランジスタ、電界効果
トランジスタ(以下FETと称す)か使用纒れX @(
8〜12.4 G Hz )あたシからはガン・インバ
ットダイオードが使用されている。
Oscillators and amplifiers using microwave integrated circuits are manufactured in the range from microwave to millimeter waves, and generally, in the microwave band, bipolar transistors, field effect transistors (hereinafter referred to as FETs), or ReX @(
8-12.4 GHz) Atashi uses Gun-in-bat diodes.

第1図の発振器はガン・インバットダイオード2を使用
したもので、先端開放線路を利用した共振器1 (一般
には2n+1/4波長線路、但しn=0、1.2.3−
)でほぼ決足される周波数の波を高周波出力としてイン
ピーダンス変成器4.直流カット用結合想路3.ザーキ
ュレータ6全介して出力を取り出している。この場合ガ
ン・インバットダイオード2のバイアス回路5はガン・
インパットダイオード20周辺、例えば第1図の場合は
共振器1の所に持っている。この為第3図に示すインビ
ータ特性の如くバイアス回路5の有無により特性が異な
る。特に点線のループ状の所ではバイアス電圧を変化し
た場合発振周波畝のジャンプが発生するのでこの影響を
考ガせねばならず、又バイアス回路5による影響ヲ極力
少なくするために帯域阻止P波器の次it多くせねばな
らない欠点がある。第1図の場合はチ衷−り、コンデン
サ。
The oscillator shown in Fig. 1 uses a Gunn-invat diode 2, and a resonator 1 using an open-ended line (generally a 2n+1/4 wavelength line, however, n=0, 1.2.3-
) is used as a high-frequency output by an impedance transformer 4. Connecting path for DC cut 3. Output is taken out through all of the circulators 6. In this case, the bias circuit 5 of the gun inbutt diode 2 is
The impact diode 20 is placed around the resonator 1, for example in the case of FIG. Therefore, the characteristics of the inbeater as shown in FIG. 3 differ depending on whether or not the bias circuit 5 is provided. In particular, in the loop shown by the dotted line, if the bias voltage is changed, a jump in the oscillation frequency ridge will occur, so this effect must be taken into consideration, and in order to minimize the influence of the bias circuit 5, a band-stopping P-wave filter is used. There is a drawback that you have to do more than that. In the case of Figure 1, it is a capacitor.

チ日−りと3段なっている。There are three tiers.

第2図はFET1使用した増巾器の例で入力よシの信号
はサーキュレータ13.直流カット用結合線路17.入
力整合回路9全介しFET8に人力し、増巾されて、出
力整合回路lO1直流カット用結合線路18.サーキュ
レータ14’t−介して出力信号を取り出している。こ
の場合FET8のゲート端子及びドレイン端子に電源を
供給するバイアス回bii、12はFET8のノー辺に
設けている。従って入力及び出力輩付器9.10を設計
する場合、バイアス回路11.12の影響を考慮する必
要がちない欠点がおる。第2図の場合チョーク、コンデ
ンサ、チB−りど3段になっている。
Figure 2 is an example of an amplifier using FET1, and the input signal is passed through circulator 13. Coupled line for DC cut 17. The input matching circuit 9 is connected to the FET 8 through the entire input matching circuit 9, and is amplified, and the output matching circuit 1O1 is connected to the DC cut coupling line 18. The output signal is taken out through the circulator 14't. In this case, the bias circuit bii, 12 for supplying power to the gate terminal and drain terminal of the FET 8 is provided on the no side of the FET 8. Therefore, when designing the input and output booster 9.10, there is a drawback that it is not necessary to consider the influence of the bias circuit 11.12. In the case of Figure 2, there are three stages: choke, capacitor, and circuit board.

(c)  発明の目的 本発明の目的は上記の欠点をなくシ、バイアス回路が半
導体素子への影響を及ぼさずかつバイアス回路の帯域阻
止p波器の次数を小さく出来るマイクロ波集積回路の提
供におる。
(c) Object of the Invention An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a microwave integrated circuit in which the bias circuit does not affect the semiconductor elements and the order of the band-stop p-wave filter of the bias circuit can be reduced. is.

(dl  発明の構成 本発明は上記の目的を達成するために、半導体素子にバ
イアスを加えるバイアス回路をサーキュレータの該半導
体素子からの入出力部と接続されない端子部に設けたこ
とを特徴とする。
(dl) Structure of the Invention In order to achieve the above object, the present invention is characterized in that a bias circuit that applies a bias to a semiconductor element is provided at a terminal portion of the circulator that is not connected to an input/output portion from the semiconductor element.

(el  発明の実施例 以下本発明の実施例につき図に従って説明する。(el Embodiments of the invention Embodiments of the present invention will be described below with reference to the drawings.

第4図は本発明の実施例の発S器の平面図、第5図は本
発明の実施例の増巾器の平面図である。
FIG. 4 is a plan view of an oscillator according to an embodiment of the present invention, and FIG. 5 is a plan view of an amplifier according to an embodiment of the present invention.

図中第1図、第2図と同一機能のものは同一記号で示す
。1′は共振器、5’、5“、 ll’、 11“、1
2’。
Components having the same functions as those in FIGS. 1 and 2 are indicated by the same symbols. 1' is a resonator, 5', 5", ll', 11", 1
2'.

12“はバイアス回路、 6’、 13’、 14’ 
はサーキュレータを示す。
12" is a bias circuit, 6', 13', 14'
indicates a circulator.

サーキュレータは外部回路とのアイル−ショノをとるた
めのものでちり、第4図の場合ではサーキーレータ6′
の出力側にバイアス回路5′搭設けても又はダミーロー
ド7fl!lにバイアス回路5′金設置プでもノノン・
インバットダイオード2への影響はない点に着目し、サ
ーキュレータ6′の出力側と直流力、ト用結合線路3と
の間にバイアス回路5″を設置プるか、サーキーレータ
6′のダミーロード711!1にバイアス回路5”を設
けILばガン−インバットダイオード2への影響はなく
なるので、バイアス回路のことは考慮せずに発振器の設
計は出来るし、又バイアス回路の帯域阻止r波器の段数
を減することがbj来る0湧4図の場合はチョーク1段
となりている。
The circulator is used to connect the external circuit, and in the case of Fig. 4, the circulator is 6'.
Even if a bias circuit 5' is installed on the output side of the dummy load 7fl! Even if the bias circuit 5' gold is installed on l.
Focusing on the fact that there is no effect on the invat diode 2, either install a bias circuit 5'' between the output side of the circulator 6' and the coupling line 3 for DC power or If a bias circuit 5" is provided in the bias circuit 5", the influence on the gun-imbat diode 2 will be eliminated, so the oscillator can be designed without considering the bias circuit. In the case of 4th figure, where the number of steps can be reduced, the choke is 1 step.

第5図の揚台は、発振器の場合と同一理由によ、9、F
E・T8のゲートのバイアス回路は入力15号の直流カ
ット用結合線路17とサーキュレータ13′如く設け、
FET8のドレインのバイアス回路は出力信号側の直流
カン) 珀合稚路18とサーキュレータ14′の出力側
の間にバイアス回路12″の如く設けるか、又はサーキ
ュレータ14′のダミーロード16側にバイアス回路1
2’の如く設ければFET8への影響はなくなるし、又
帯域阻止ν波器の次数を減することが出来る。第5図の
場合はチョーク1段となっている。
For the same reason as the oscillator, the platform in Figure 5 is 9, F
The bias circuit for the gate of E/T8 is provided like the DC cut coupling line 17 of input No. 15 and the circulator 13'.
The bias circuit for the drain of FET 8 is provided as a bias circuit 12'' between the output side of the output signal side (DC circuit on the output signal side), or the bias circuit is provided on the dummy load 16 side of the circulator 14'. 1
If it is provided like 2', there will be no influence on the FET 8, and the order of the band-elimination ν wave filter can be reduced. In the case of Fig. 5, there is one stage of choke.

(f)  発り2〕の効果 以上詳細iCC開明る如く本先明によれば、バイアス回
路は半纏体米子への影響がなくなるので発振器の設計又
は増巾器の場合は半導体素子の入出力の整合回路の設計
が楽にな9又バイアス回路の帯域阻止f波器の次数を減
することが出来る効果がある。
(f) Effects of Origin 2] In detail, according to the present invention, the bias circuit has no influence on the semi-integrated body Yonago, so in the case of the oscillator design or the amplifier, the input/output of the semiconductor element can be improved. This has the effect of making it easier to design the matching circuit and reducing the order of the band-stop f-wave filter in the nine-way bias circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例の発振器の平面図、第2図は従来例の増
巾器の平面図、第3図は第1図のガン・インバットダイ
オードの位置より見た外部回路のインピーダンス特性図
、第4図は本発明の実施例の発振器の平面図、第5図は
本発明の実施例の増巾器の平面図である。 図中1.1′は共振器、2はガン・インバットダイオー
ド、3.17.18は直流カット用結合線路。 4はインピーダンス変成器、 5.5’、 5″、 1
1.11’。 11″、 12.12’、 12″はバイアス回路、 
6.6’、13゜13’、14.14’は・す°−キュ
レータ、7.15.16はダミーロード、8は電界効果
トランジスタ、9は人力整合上i路、10は出力整合回
路を示す。 矛/y Pz図 矛3図
Fig. 1 is a plan view of a conventional oscillator, Fig. 2 is a plan view of a conventional amplifier, and Fig. 3 is an impedance characteristic diagram of the external circuit as seen from the position of the gun-imbat diode in Fig. 1. , FIG. 4 is a plan view of an oscillator according to an embodiment of the present invention, and FIG. 5 is a plan view of an amplifier according to an embodiment of the present invention. In the figure, 1.1' is a resonator, 2 is a gun-imbat diode, and 3.17.18 is a coupled line for DC cutting. 4 is an impedance transformer, 5.5', 5'', 1
1.11'. 11″, 12.12′, 12″ are bias circuits,
6.6', 13°13', 14.14' are the curators, 7.15.16 are the dummy loads, 8 is the field effect transistor, 9 is the i-way for manual matching, and 10 is the output matching circuit. show. spear/y Pz spear 3

Claims (1)

【特許請求の範囲】[Claims] 半導体素子と種々の回路全集積したマイクロ波集積回路
よりなる発振器又は増巾器において、該半導体素子にバ
イアスを加えるバイアス回路をサーキュレータの該半導
体素子の人出力部と接続されない端子部に設けたことを
%徴とするマイクロ波集積回路。
In an oscillator or amplifier made of a microwave integrated circuit in which a semiconductor element and various circuits are fully integrated, a bias circuit for applying a bias to the semiconductor element is provided in a terminal part of the circulator that is not connected to the human output part of the semiconductor element. Microwave integrated circuit with % characteristics.
JP13757182A 1982-08-07 1982-08-07 microwave integrated circuit Pending JPS5951601A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13757182A JPS5951601A (en) 1982-08-07 1982-08-07 microwave integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13757182A JPS5951601A (en) 1982-08-07 1982-08-07 microwave integrated circuit

Publications (1)

Publication Number Publication Date
JPS5951601A true JPS5951601A (en) 1984-03-26

Family

ID=15201826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13757182A Pending JPS5951601A (en) 1982-08-07 1982-08-07 microwave integrated circuit

Country Status (1)

Country Link
JP (1) JPS5951601A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63501675A (en) * 1985-10-03 1988-06-23 ヒユ−ズ・エアクラフト・カンパニ− Broadband high isolation radial line power splitter/combiner

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5619901B2 (en) * 1976-06-23 1981-05-11

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5619901B2 (en) * 1976-06-23 1981-05-11

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63501675A (en) * 1985-10-03 1988-06-23 ヒユ−ズ・エアクラフト・カンパニ− Broadband high isolation radial line power splitter/combiner

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