JPS5949580A - Manufacture of matrix display panel - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a reflective matrix display panel with an enlarged pixel effective area.

Conventional configuration and its problems In order to display a matrix on a liquid crystal display with a low duty ratio,
There has been an attempt to introduce a Nuinch element made of a thin film transistor (hereinafter abbreviated as TPT) into each picture element. That is, the first
As shown in the plan view of the figure and the AA' sectional view of Figure 2, T
A substrate 10 with an FT array is formed by forming a layer 1, an electrode 1, a gate insulating film 2, etc. on an insulating substrate 7 made of glass or the like. Semiconductor layer 3. Drain electrode 4, source electrode 6. A picture element electrode 8 is configured for each picture element. The drain electrode 4 is connected to the picture element electrode 8 via a contact hole (V9) provided in the gate insulating layer 2.

As shown in FIG. 3, the TFT array-equipped substrate 1o of FIG. 1 and indium oxide,
By sandwiching a display medium 12 such as a liquid crystal between a substrate having a transparent common electrode 13 made of tin oxide or the like, an XY matrix display panel capable of displaying a large number of picture elements can be constructed.

FIG. 4 shows an electrical equivalent circuit of the matrix display panel with TPT array shown in FIGS. 1 to 3. The operating principle will be explained below based on FIGS. 1, 2, and 4.

For convenience, the TFT 11 is considered to be an n-channel enhancement type using CdSe or amorphous silicon as a semiconductor layer. In this case, when a voltage is applied to the drain electrode 4 so that it is positive with respect to the source electrode 5, and the gate electrode 1 is kept at a potential equal to or lower than the source electrode 6, the TFT 11 is turned off. , almost no current flows between the source and drain, but the gate voltage J'! I
(If 1 is kept positive with respect to the source electrode 5, electrons are induced into the semiconductor film in contact with the gate insulating film, resulting in TFT 11
turns on, and current flows between the source and drain. In the case of matrix driving, signals are normally applied line sequentially. For example, FIG. 6(a) shows an example in which AC driving is performed using a liquid crystal as a display medium.

Shown in (b). The voltage waveforms on the scanning side (Y+ to Ys) and the signal side (X1 to X5) when performing the 3×3 dot matrix display shown in FIG. 5(b) are shown in FIG. 5(a).
In FIG. 5(b), on-cells are indicated by diagonal lines.

As mentioned above, in the conventional matrix display panel with TPT array, as is clear from FIG. 8 except for the contact holes. That is, the effective area of the picture element is significantly deteriorated due to the Saone electrode 5 and the gate electrode 1. In particular, even if the pixel density becomes high, the pattern shown in Figure 1 cannot be reduced in a similar manner.

This is because as the width of the source and gate electrodes becomes narrower, wiring resistance increases and defects such as broken wires that distort signal waveforms are more likely to occur. This will further reduce the ratio of the effective area of the picture element, and the electrode configuration shown in Figure 1 is particularly important for high-resolution displays, as it will seriously degrade the display quality and lead to a decrease in macroscopic contrast. This was a problem.

OBJECTS OF THE INVENTION In order to overcome the following drawbacks of the prior art, the present invention provides a method for manufacturing a matrix display panel, which improves the array manufacturing process and expands the effective area of pixels while employing a simplified process. It provides:

Structure of the Invention The manufacturing method of the present invention includes: (1) providing a gate electrode to serve as a first electrode on an insulating substrate; (2) providing a gate insulating layer in a peripheral area of the insulating substrate except for a terminal extraction portion; , ■ providing a semiconductor layer on the gate insulating layer in approximately the same shape as the semiconductor layer; ■ providing a protective insulating layer in approximately the same shape as the semiconductor layer; ■ providing a drain contact hole in the protective insulating layer. Steps: -Providing a second electrode film on almost the entire surface including the protective insulating layer; ■Changing the second electrode film into the shape of source and drain electrodes; ■Providing the source and drain electrodes. (1) providing a pixel contact hole in the interlayer insulating layer; [phase] forming a third layer on the surface including the interlayer insulating layer;
T (step of providing an I electrode film, ■ step of converting the third electrode film into the shape of a pixel electrode, 0 a surface of the substrate having the pixel electrode and a transparent common layer provided on the transparent insulating substrate) This includes the steps of sandwiching a display medium between the electrodes.

In the present invention, since the semiconductor layer is used in a continuous phase state without any reduction in size, the effective area of the picture element is expanded, and the conventional semiconductor layer can be made into minute parts.
This solves the disadvantages of the method of providing in minute parts, which is that the number of steps is increased, and that this step tends to cause variations in device characteristics and a decrease in yield.

Description of examples An embodiment of the present invention will be described below with reference to the drawings.

In the manufacturing method of the present invention, first, a gate electrode material such as chromium, nichrome, molybdenum, or gold is formed on an insulating substrate such as glass, and then a gate electrode material such as chromium, nichrome, molybdenum, gold, etc. is formed using a first photomask as shown in FIG.
As shown in the plan view of &) and the BB' cross-sectional view of FIG. 6(b), the gate electrode 1 is formed into a pattern. (Usually, the common electrode terminal 1 is used to take out the common electrode 13 on the same substrate γ.
3 is provided, but its illustration is omitted in the following drawings. ) Next, as shown in FIGS. 7(a) and 7(b), if an amorphous silicon TPT is fabricated by, for example, the plasma CVD method, the substrate is placed in a plasma reactor, and a mixed gas containing silanganu as a main component is injected into the plasma. A gate insulating film 2 of silicon nitride, silicon oxide, or the like is formed by discharging. At this time, in order to eliminate the need for a process to remove the film later, a metal plate, etc., for example, is placed in close contact with the substrate around the periphery of the substrate having the gate so that no film is deposited on the terminal portion 15. Then, plasma discharge is performed. Next, the Ganu composition is changed and plasma discharge is performed again using Silanganu as a component to deposit the amorphous silicon semiconductor film 3 in the same shape as the gate insulating film. After forming a protective insulating film 1B on this, source and drain contact holes 19 and 20 are formed by photo-etching as shown in FIG. Next, as shown in FIGS. 8(2L) and 8(b), a second electrode film is provided on almost the entire surface of the substrate by vapor deposition, nupatsu, etc., and then, by step 1) etching, it is deposited on the source electrode 5 and drain electrode 4. become Next, Figure 9(a)
, As shown in (b), the first step is to deposit an organic insulating film such as a resist or polyimide film or vapor deposition.

An inorganic insulating film such as sialumina, silicon dioxide, silicon nitride, etc. is provided as the interlayer insulating film 21 by the Schutter, CVN method, or the like. A contact hole 22 for a picture element electrode is provided in the interlayer insulating film by photo-etching.

Next, as shown in FIGS. 10(&) and 10(b), a metal film that will become a pixel electrode is formed on almost the entire surface of the substrate by vapor deposition or by sottering, and the shape of the pixel electrode 8 is formed by photoetching. to slam.

Although the TPT manufacturing process of the present invention has been explained above based on the plasma CVN method, different gate insulating films 2, semiconductor films 3 (cadmium selenide, tellurium, etc.), interlayer insulating films, etc. can be formed using vapor deposition or sputtering methods. The structure is the same when using .

In any case, the transparent electrode 1q of the substrate 14, such as glass or plastic, having a transparent electrode, and the TP manufactured as described above.
A display medium is inserted between the T-array and the T-array as shown in FIG. 3 to form a display panel.

Various types of display media 12 can be used as the display medium 12 used in the present invention, but in particular, when the picture element electrode is an opaque reflective electrode such as aluminum, a nematic liquid crystal or a mixed liquid crystal of nematic liquid crystal and cholesteric liquid crystal has dichroism. A small amount of ionic dopant is added to a nematic liquid crystal with negative dielectric anisotropy, which is used in the so-called guest-honuto mode, in which a dye is dissolved, and an electric field is applied to form scattering nuclei to make the liquid crystal cloudy. A so-called DSM mode liquid crystal, a so-called phase change liquid crystal in which an electric field is applied to a mixture of a nematic liquid crystal and a cholesteric liquid crystal to cause a phase change between a nematic phase and a cholesteric phase, thereby realizing a transparent or cloudy display, can also be used. On the other hand, in devices other than liquid crystals, for example, so-called electrophoretic display dispersion systems in which pigment particles of a different color are dispersed in an organic solvent colored with a dye, electrochromic display media, electroluminescence display media, etc. According to the manufacturing method, the source electrode 5 and the goo 1-electrode 1 are isolated by the gate insulating layer 2, the semiconductor layer 3, and the protective insulating layer 18, so that crossover insulation is maintained. Further, the picture element electrode 8 and the source electrode 5 are separated by an interlayer insulating layer 18, and the gate electrode 1 and the picture element electrode 8 are separated from a large number of insulating layers and the semiconductor device, so that electrical insulation is maintained sufficiently. Therefore, the picture element electrode 8 can be made larger than the conventional one by the amount of overlap with the source electrode 5 and the gate electrode 2, and the effective area of the picture element can be made larger in the wooden sword type display panel than in the conventional manufacturing method. can be significantly improved.

In the present invention, an improved configuration for further improving the performance of the TPT array will be described below.

That is, instead of providing only the gate electrode on the substrate prior to forming the gate insulating film, a common electrode 17 for forming parallel capacitance is simultaneously formed as shown in FIG. 11. This can be achieved by simply changing the pattern of the photomanuk as shown in FIG. 11 without increasing the number of steps. The following is exactly the same process as mentioned at the beginning.
A T-array is formed.

Common 71 for forming the parallel capacitance! Ju17 is display medium 1
Before or after sandwiching the display medium 12, the display medium 12 is electrically connected to the common transparent electrode 13 sandwiching the display medium 12, thereby completing the panel. In this case, the gate insulating layer 2, the semiconductor layer 3, and the interlayer insulating layer 18 are sandwiched in a laminated manner between the parallel capacitance forming common electrode 17 and the picture element electrode 8 to form a capacitor. Also, since the common electrode for forming parallel capacitance and the common transparent electrode are electrically connected, they are electrically added in parallel with the pixel capacitance formed here, hence the name parallel capacitance. .

When a pixel parallel capacitor is added to a TPT array, there are advantages such as being able to use a low resistance display medium, being able to drive at a low voltage, and being able to use a TPT with a relatively low off-resistance.

As mentioned above, the present array forming method is particularly practical in that it can easily produce the advantages described above without adding any special process to the process of the present invention described in FIGS. 6 to 10. It can be said that the value is high.

Effects of the Invention What is important in the present invention is that in conventional TPT array formation, a semiconductor layer is provided over the entire surface and then divided into small portions by photo-etching, or micro-layers are formed using a vapor deposition mask or the like in advance. In contrast to the conventional method of forming a semiconductor layer only in a small portion, the present invention has a method of forming a semiconductor layer into minute portions or forming a semiconductor layer in a minute portion, which requires an additional step and changes the device characteristics in this step. Focusing on the fact that the semiconductor layer tends to have variations and a decrease in yield, the semiconductor layer is designed to be used in a continuous phase without being miniaturized at all. Therefore, in order to expose the electrode terminals and edges, it is recommended to apply a shielding mask only to this area when forming the insulating layer or semiconductor layer in order to prevent the insulating layer or semiconductor layer from being formed in this area. Fortunately, film formation on unnecessary areas can be prevented without increasing the number of steps.

On the other hand, a protective insulating layer 1 is provided in the TPT channel region 16 (FIG. 8), and a semiconductor layer 3 is provided on the display medium 12.
Another great advantage is that TPT is stable over a long period of time because it is protected without direct contact with the TPT.

A further important advantage of the present invention is that it ensures that the TPT channel section 16 is shielded from light.

Generally, amorphous silicon, cadmium hydroxide, etc.
The semiconductor film 3 for FT has photoconductivity and its characteristics change depending on the surrounding brightness, but in the configuration of the present invention, the opaque picture element electrode covers the channel part of the TPT and has a light shielding effect. It can be used under stable characteristics.

[Brief explanation of drawings]

Figure 1 is an enlarged plan view of the main part of a conventional matrix display panel JT/TPT array, Figure 2 is a cross-sectional view taken along A-A' in Figure 1, and Figure 3 is a 7-trix display with TFT array. A sectional view of the panel, FIG. 4 is an electrical equivalent circuit diagram of the matrix display panel with TPT array in FIG. 3, and FIG.
), (b) is a waveform diagram and a schematic diagram explaining the driving of each cell of the matrix display panel, and each of FIGS.
(shi) is a plan view of a main part and a sectional view taken along line BB' for explaining each step of the manufacturing method of the present invention, and FIG. 11 is a TPT array formation used in the further improved manufacturing method of the present invention. FIG. DESCRIPTION OF SYMBOLS 1... Gate electrode, 2... Gate insulating layer, 3... Semiconductor layer, 4... Drain electrode, 6... Source electrode, 7... Board, 8
...Picture element electrode, 13...Transparent common electrode, 14...Glass substrate, 15...Terminal,
16...TFT channel area, 17...
...Common electrode for parallel capacitance formation, 1st...Protective insulating layer, 19...Drain contact hole/L'
, 20・−・・−・Source contact 1-hole, 21・
. . . Interlayer insulating layer, 22 . . . Picture element contact hole. Name of agent Patent attorney Toshio Nakao and 1 other person [''- ff15 Figure Cα) ('tn Figure 7 (α)

Claims (2)

[Claims] (1) ■Providing a gate electrode, which will become the first electrode, on the insulating substrate; ■Providing a gate insulating layer in the peripheral area of the insulating substrate except for the terminal extraction portion; and ■On the gate insulating layer. (1) providing a protective insulating layer in approximately the same shape as the semiconductor layer; (2) providing source and drain contact holes in the protective insulating layer; (2) providing the protective insulating layer in the protective insulating layer. a step of providing a second electrode film on almost the entire surface including the source and drain electrodes; (1) providing a pixel contact hole in the interlayer insulating layer; [phase] providing a third electrode film including the interlayer insulating layer; (2) forming the third electrode film into a pixel electrode. [Phase] A step of sandwiching a display medium between the surface of the substrate having picture element electrodes and a transparent common electrode provided on a transparent insulating substrate. A method of manufacturing a 71 helix display spring. (2) In the first step, an electrode for forming a storage &1 capacitor is provided in addition to the gate electrode (jr), and a storage capacitor is formed between it and the drain electrode provided in the seventh step. A method for manufacturing a 7-trix display panel according to claim (1).